A new application of Ant Colony Optimization (ACO) called improved-EAS (i-EAS) is proposed for solving the function optimization problem. i-EAS is an improvement on the elitist ant system (EAS) which was devised to solve the Travelling Salesman Problem (TSP). It is capable of stepwise localization of the search space. Here, we examined methods that search for solutions in the real space Rn by approximating them using discrete values (binary data). Our proposed ACO uses stepwise localization of the search space to improve the accuracy of solutions. To localize the search space on the current step, our ACO searches for solutions recursively in neighbors of the best solution β found on the previous step. We assume that α is the number of times that the search space is localized, then we reduce the search space so that R(α) satisfies the equation R(α) = RANGE × (1 / 2)(α × ln α), where RANGE is provided as an initial value. Although the domain of each independent variable is reduced, the number of observable points is 2l and does not change according to α, which means that solution accuracy can be improved so that d(α) = RANGE × (1 / 2)(α × ln α)+l-1, where d(α) is the interval of the observable data. To improve solution accuracy further, we perform mutation operations on the solution found by each ant every time it finishes a tour in search of solutions. Furthermore, in order to maintain population diversity, we dynamically altered the weight of elitist ant pheromone cyclically. The validity of i-EAS is verified by using well-known standard test functions with multiple peaks.

Due to latest advances in semiconductor integration, systems are becoming more susceptible to faults leading to temporary or permanent failures. We propose a new architecture extension suitable for arrays of functional units (FUs), that will provide testing and replacement of faulty units, without interrupting normal system operation. The extension relies on data-path switching realized by the proposed hot-swapping algorithm and structures, by use of which functional units are tested and replaced by spares, at lower overheads than traditional modular redundancy. For a case study architecture, hot-swapping support could be added with only 29% area overhead. In this paper we focus on experimental evaluation of the hot-swapping system from a fabricated chip in 65nm CMOS process. Autonomous testing of the hot-swapping system is enhanced with back-bias circuitry to attain an early fault detection and restoration system. Experimental measurements prove that the proposed concept works well, predicting fault occurrence with a configurable prediction interval, while power measurements reveal that with only 20% power overhead the proposed system can attain reliability levels similar to triple modular redundancy. Additionally, measurements reveal that manufacturing randomness across the die can significantly influence identical sub-circuit reliability located in different parts in the die, although identical layout has been employed.

JPEG XR is an emerging image coding standard, based on HD Photo developed by Microsoft Corporation. It supports high compression performance twice as high as the de facto image coding system, namely, JPEG, and also has an advantage over JPEG 2000 in terms of computational cost. JPEG XR is expected to be widespread for many devices including embedded systems in the near future. In this article, we propose a novel architecture for JPEG XR encoding. In previous architectures, entropy coding was the throughput bottleneck because it was implemented as a sequential algorithm to handle data with dependency. We found that there is no dependency in intra-macroblock data, and we could safely pipeline all the encoding processes including the entropy coding. In addition, each module of our architecture, which can be regarded as a pipeline stage, can be parallelized. As a result, our architecture can achieve 12.8 pixel/cycle at its maximum. To demonstrate our architecture, we designed three versions of our architecture with different degrees of parallelism of one, two, and four. Our four-way parallel architecture achieves 579 Mpixel/sec at 181MHz clock frequency for grayscale images.

We propose a design and control of an air pillow system (IAAP: Impedance Adjustable Air Pillow), in which users can independently adjust its height and tactile sensation. The IAAP consists of an air bag with a pressure sensor and a motor-driven piston-cylinder mechanism. Because the IAAP does not contain any mechanical sensors inside the air bag, by using only the air pressure and the piston position, we propose an impedance control method to set the target impedance (rigidity and viscosity) of the air bag. To evaluate the usability of our IAAP, some sensory evaluation tests were carried out on a group of subjects. As a result of the tests, we conclude the IAAP has a good practical potential as a high-performance pillow for comfortable sleep.

Due to latest advances in semiconductor integration, systems are becoming more susceptible to faults leading to temporary or permanent failures. We propose a new architecture extension suitable for arrays of functional units, that will provide testing and replacement of faulty units, without interrupting normal system operation. The extension relies on data path switching controlled by a hot-swapping algorithm, by use of which functional units are tested and replaced by spares if necessary, ensuring permanent operation while the spares last. The Hot-Swapping functionality could be added as a case study on a sample architecture, with an overhead of 74-87%. Also, a prototype chip (4.2 mm times 2.1 mm) targeted to operate at 166 MHz has been fabricated, using 65 nm process technology.

Emerging high-speed mobile networks enable us to receive media streaming data by mobile terminals on demand. However, media streaming with fixed bitrate causes some problems such as annoying artificial noise, interruption, and so forth, since link quality fluctuates dramatically in such mobile networks. Motivated by this, in this paper, we propose a novel media streaming system with dynamic rate control scheme to achieve continuous streaming on such unstable networks. The proposed rate control scheme uses the delay of the transcoding process to estimate network bandwidth, and adjusts the bitrate of media streams dynamically. To demonstrate our system and scheme, the proposed streaming system is evaluated under some typical models of bandwidth change in high-speed mobile networks. The results show that stable and high-quality streaming without interruption can be achieved by the proposed scheme. Moreover, we successfully demonstrate that our system performs continuous streaming on real mobile networks even in the severe network condition such as on a moving train.

In this paper, a prototype implementation of stream- ing system that allows listening to and viewing multimedia contents using a mobile terminal, as part of our efforts toward realizing services linked with home networks and mobile net- works is presented. In our system, appliances are detected and connected to a mobile terminal by use of peer-to-peer (P2P) network based on the PUCC protocols, and they are controlled by use of P2P messages and IEEE1394 AV/C. Streaming is managed by a gateway on the P2P network, where multimedia contents are converted to another format suitable to be sent to mobile terminals. This prototype system successfully achieves video data streaming over two different networks by using P2P network which conceals the differences among the networks.

Robust and rapid object detection is one of the great challenges in the field of computer vision. This paper proposes a hardware architecture suitable for object detection by Viola and Jones based on an AdaBoost learning algorithm with Haar-like features as weak classifiers. Our architecture realizes rapid and robust detection with two major features: hybrid parallel execution and an image scaling method. The first exploits the cascade structure of classifiers, in which classifiers located near the beginning of the cascade are used more frequently than subsequent classifiers. We assign more resources to the former classifiers to execute in parallel than subsequent classifiers. This dramatically improves the total processing speed without a great increase in circuit area. The second feature is a method of scaling input images instead of scaling classifiers. This increases the efficiency of hardware implementation while retaining a high detection rate. In addition we implement the proposed architecture on a Virtex-5 FPGA to show that it achieves real-time object detection at 30 frames per second on VGA video.

Reconfigurable devices are expected to be utilized in the mission-critical fields such as space development, because a system update and a pseudo-repair can be achieved remotely by reconfiguration. However, conventional reconfigurable devices suffer from memory bit upsets caused by charged particles in space that result in fatal system troubles.This paper proposes an autonomous repair mechanism against configuration upsets for fault-tolerant reconfigurable devices. In proposed architecture, devices consist of 'Autonomous-Repair Cells' with built-in (not reprogrammable) error recovery circuits. Each cell realizes a part of the system's functionality, and guarantees fault tolerance against upset of its own configuration memory. In this paper, four types of Autonomous-Repair Cells are designed and then average lifetime is analyzed. Two of cells are based on TMR (Triple Module Redundancy) and the others are based on EDAC (Error Detection and Correction). In a severe situation where a conventional reconfigurable device with 1Mbit configuration data can achieve only 1-minute average lifetime against configuration upsets, all proposed cells can achieve more than 100 years.

Reconfigurable devices are expected to be utilized in the mission-critical fields such as space development, because a system update and a pseudo-repair can be achieved remotely by reconfiguration. However, conventional reconfigurable devices suffer from configuration memory upsets caused by radiation in space. This paper proposes an architecture of a fault-tolerant reconfigurable device based on island-style FPGA. The device consists of "autonomous-repair cells" which repairs these upsets autonomously and dynamically. To determine the architecture, we analyze four autonomous repair techniques of the cell experimentally. Then, optimal autonomous repair techniques are applied to both of programmable logics and cell-to-cell routing resources. Through evaluation, we show that proposed device achieves more than 10 years average lifetime against configuration upsets even in a severe situation such as a satellite orbit

In this paper, an automated design method of digital filters for 3-D sound localization is proposed, which approximates head-related transfer function (HRTF). Target digital filter organization is dedicated for embedded applications so that ROM capacity and computational load are reduced with only a slight degradation of 3-D sound effect. The proposed design method consists of two steps. In the first step, the least-squares method is adopted to acquire initial design result quickly, while the second step utilizes the gradient search algorithm for precise optimization. In an objective evaluation, the proposed two-step method is proved to be effective for improving design results. Results of subjective listening tests also show that the proposed method is comparable to manual design in the approximation of reference HRTF. In these subjective tests, our automated design achieved better results per ROM capacity than simple FIR filter did

A novel pedestrian tracking scheme based on a particle filter is proposed, which adopts a skeleton model of a pedestrian as a state space model and uses distance transformed images for likelihood estimation. The six-stick skeleton model used in the proposed approach is very distinctive in representing a pedestrian simply but effectively, with which the efficient state space for the pedestrian tracking can be derived. Experimental results by using PETS sample sequences demonstrate that the proposed approach achieves highly accurate pedestrian tracking without any of prior learning.

An encoding/decoding process of JPEG2000 requires much more computation power than that of conventional JPEG mainly due to the complexity of entropy encoding/decoding. Thus usually multiple entropy codec hardware modules are implemented in parallel to process entropy encoding/decoding. This module, however, requests many small-size memories to store intermediate data, and when multiple modules are implemented on a chip, employment of the large number of SRAMs increases difficulty of whole chip layout. In this paper, an efficient memory architecture of the entropy encoding/decoding module is proposed, in which three approaches are attempted by utilizing one-bank SRAMs and internal registers. As a result, the efficient memory organization for a target process technology can be explored

To cope with the recent mobile scenes where images are used aggressively, a novel rate control scheme is proposed. The proposed scheme, dedicated for JPEG2000 image coding, aims at achieving low computational cost and small working memory size while maintaining high image quality. By predicting the adequate number of coding passes and updating it adaptively in code-block coding, the proposed scheme reduces both computational cost and working memory size for bitstream buffering down to 29% and 13%, respectively.

We consider a teaching system that covers the stages of task from planning to on-site teaching, and propose for it a structured description based on task properties. A multimodal communication-teaching-advisor (MCTA) system is used for on-site teaching for a tool-manipulating task. The modular structure and object-oriented task handling program enable it to be applied to various robot systems and lets system developers customize the interface easily. The interface allows the operator and robot to share internal and external sensor data via nonverbal media. The intentions of an inexpert operator, who has only common knowledge and ordinary abilities, can then be transferred to the robot system via nonverbal operation. Experiments show that two different types of robot controller could be controlled by this teaching system, and the nominal task program was designed for an environment with two controllers.

The development of robot systems must be simplified and made less expensive so that they can be used more widely in various industrial fields. We propose a component architecture of a robot-teaching system based on a universal task model, that enables fast and easy development of robot-teaching systems for various types of work.

The previously proposed multimedia-communication (MC) robot-teaching pendant interface has been given an improved interface function and has been implemented into a modular system structure. The modular structure enables it to be applied to various robot systems, and the improved interface enables the operator and robot to share internal and external sensor data via nonverbal media. The intentions of an operator with only common knowledge and abilities can then be transferred to the robot via nonverbal operation. Using the MC pendant interface, the operator sets the situation-dependent sensor-process parameters by sketching a profile over a graphical display of the shared sensor data. This requires only a simple pattern-recognition ability. Experiments showed that novice operators with no special task knowledge can set appropriate parameters for the given task conditions.

A robot task design system for robot tool manipulation tasks is proposed and implemented. The system consists of an on-site object modeling system and a task attribute design system. The on-site object modeling system is an online measurement system that obtains the local object geometry. The task attribute design system is an off-line system that describes the tool operation along the task path on the object. It provides a high-level task description suitable for human understanding of the task via a graphical user interface. This system has been successfully applied to a deburring robot system equipped with a laser range sensor.

A methodology for generating an optimum software quality classification tree using software complexity metrics to discriminate between high-quality modules and low-quality modules is proposed. The process of tree generation is an application of the AIC (Akaike Information Criterion) procedures to the binomial distribution. AIC procedures are based on maximum likelihood estimation and the least number of complexity metrics. It is an improvement of the software quality classification tree generation method proposed by Porter and Selby (1990) from the viewpoint that the complexity metrics are minimized. The problems of their method are that the software quality prediction model is unstable because it reflects observational errors in real data too much and there is no objective criterion for determining whether the discrimination is appropriate or not at a deep nesting level of the classification tree when the number of sample modules gets smaller. To solve these problems a new metric is introduced and its validity is theoretically and experimentally verified. In our examples, complexity metrics written in C language, such as lines of source code, Halstead's (1977) software science, McCabe's (976) cyclomatic number, Henry and Kafura's (1981) fan-in/out and Howatt and Baker's (1989) scope number, are investigated. Our experiments with a medium-sized piece of software (85 thousand lines of source code; 562 samples) show that the software quality classification tree generated by our new metric identifies the target class of the observed modules more efficiently using the minimum number of complexity metrics without any significant decrease of the correct classification ratio (76%->72%) than the conventional classification tree.

The paper explains how to evaluate software maintainability by considering the effects of interfaced complexities between modified and unmodified parts. When software is maintained, designers develop software, considering not only functions of modified parts but also those of unmodified parts by reading specifications or source codes. So, not only does the volume and complexity of the unmodified and modified parts, but also the interfaced complexities between, them greatly affect the occurrence of software errors. The modified part consists of several subsystems, each of which is composed of several functionally related routines. The unmodified part also consists of several routines. A routine corresponds to a function of C-coding. We experimentally show by regression and discriminant analyses that the quality of each routine tends to decrease as the reuse-ratio increases. The optimal threshold of reuse-ratio is selected by applying AIC (Akaihe Information Criterion) procedures to discriminant analysis for software quality classification. We can reasonably separate routines into two parts, one modified in which most software errors occur and the other unmodified in which few errors occur. The interfaced complexities measured by the extended cyclomatic number between each sub system of the modified part and the unmodified part greatly affect the number of errors and error density. By applying regression analysis to medium size software, we have shown that 40% of variance of error density are represented by interfaced complexities among each subsystem of the modified part and the unmodified part.

We describe a new robot teaching interface, the multimedia communication pendant (MC Pendant) to make robots more intelligent through human support. Wide, nonverbal and bi-directional communication channels and multimedia technology allow information to be shared between operators and robots. That is information to be reflected human knowledge or perception and robot information to be perceived by humans. Experimental results show that the MC pendant improves operational accuracy and greatly reduces the time needed for teaching, compared with a conventional pendant.

The authors developed an efficient high-level synthesis and optimization system for large-scale circuits, which reduces the total number of fan-ins in the technology-independent phase and adjusts speed and area after technology mapping is completed. A description is presented of multi-level logic optimization techniques based on refined weak division methods and additional functions for carrying out good optimization with only a slight overhead. The authors also describe technology mapping and local optimization techniques suitable for high-level CAD systems. The system has shown that multi-level logic optimization in VLSIs with more than 100000 gates (that is, VLSIs whose control logic comprises more than 10000 gate circuits) is possible in practical CPU time.>

This paper describes a new designer environment and its technical features for aiding in several design phases of digital equipment, including architecture, function, and logic design. The author and his coworkers have integrated an editor of a register transfer level (RTL) behavioral language, a translator, a simulator, and evaluation and optimization tools into a single system. In addition, they have developed a hardware synthesizer which automatically produces a gate-level connective description from the RTL behavioral description. With this new environment, designers can more quickly create designs and interactively change design data in the evaluation phase. Using this behavioral-description-based CAD environment, they designed a one-LSI-chip PROLOG machine with 33 independent control parts for executing unification and backtracking algorithms. The machine operates at 130 KLIPS, and is 18 213 gates in size. It took 7.8 person-months to carry out its architecture, function, and logic design.