A lateral overflow integration capacitor (LOFIC) CMOS image sensor (CIS) can achieve high-dynamic-range (HDR) imaging by combining a low conversion-gain (LCG) signal with a high conversion-gain (HCG) signal. However, the signal-to-noise ratio (SNR) drops at the switching point from HCG to LCG due to the large pixel noise in the LCG signal. To address this issue, a triple-gain LOFIC-CIS with a middle conversion-gain (MCG) signal is introduced. In this paper, we propose an area-efficient readout circuit for the triple-gain LOFIC-CIS, utilizing amplifier-sharing and capacitor-sharing techniques to process the HCG, MCG, and LCG signals. A test chip of the readout circuit was fabricated using the 0.18 µm CMOS process, with an area overhead of only 7.6% and an SNR drop improvement of 8.05 dB compared to the readout circuit for a double-gain LOFIC-CIS.

High-definition television (HDTV) images are now commonly available and the recent trend of video applications is toward even higher spatial resolutions with higher pixel rates. To make such high-resolution video images possible, the sensor must have a line time, or one row time, of less than a few microseconds with a pixel rate greater than gigapixels per second. In this paper, the basics of complementary metal–oxide–semiconductor (CMOS) image sensors and the architectures/technologies used to obtain such high resolutions and frame rates are reviewed and the technologies to obtain the highest possible quality video images are explained.