Analog in-Memory Computing (AiMC) based on Phase-change Memory (PCM) enables highly efficient Ma-trix-vector Multiplication (MVM) for edge-AI workloads. However, sequential programming of PCM cells introduces timedependent conductance misalignments that may degrade computational accuracy, especially in large arrays. This work analyzes the impact of programming delay-induced errors in PCM-based AiMC systems. An analytical model is derived to characterize the resulting MVM error as a function of array size, programming time, and drift coefficients. Then, two mitigation techniques are proposed to mitigate the MVM error, namely Importance-Aware Scheduling (IAS) and Digital Rescale Compensation (DRC). These approaches are experimentally validated on a 512×512 PCM-based AiMC prototype, achieving up to 85% reduction of MVM error induced by the programming scheme.

The search for energy efficient circuital implementations of neural networks has led to the exploration of phase-change memory (PCM) devices as their synaptic element, with the advantage of compact size and compatibility with CMOS fabrication technologies. In this work, we describe a methodology that, starting from measurements performed on a set of real PCM devices, enables the training of a neural network. The core of the procedure is the creation of a computational model, sufficiently general to include the effect of unwanted non-idealities, such as the voltage dependence of the conductances and the presence of surrounding circuitry. Results show that, depending on the task at hand, a different level of accuracy is required in the PCM model applied at train-time to match the performance of a traditional, reference network. Moreover, the trained networks are robust to the perturbation of the weight values, up to 10% standard deviation, with performance losses within 3.5% for the accuracy in the classification task being considered and an increase of the regression RMS error by 0.014 in a second task. The considered perturbation is compatible with the performance of state-of-the-art PCM programming techniques.

Several recent works have shown the advantages of using phase-change memory (PCM) in developing brain-inspired computing approaches. In particular, PCM cells have been applied to the direct computation of matrix-vector multiplications in the analog domain. However, the intrinsic nonlinearity of these cells with respect to the applied voltage is detrimental. In this paper we consider a PCM array as the encoder in a Compressed Sensing (CS) acquisition system, and investigate the effect of the non-linearity of the cells. We introduce a CS decoding strategy that is able to compensate for PCM nonlinearities by means of an iterative approach. At each step, the current signal estimate is used to approximate the average behaviour of the PCM cells used in the encoder. Monte Carlo simulations relying on a PCM model extracted from an STMicrolectronics 90 nm BCD chip validate the performance of the algorithm with various degrees of nonlinearities, showing up to 35 dB increase in median performance as compared to standard decoding procedures.

This work presents a compensation technique for a three-stage operational amplifier that is derived from nested Miller compensation and comprises a voltage gain stage in the inner compensation path. The voltage gain k of this stage is able to both increase the Miller effect across the inner compensation capacitor and reduce the high-frequency impedance of the output node when compared to the case of standard nested Miller compensation. As a consequence, the gain-bandwidth product is k times higher, while the inner and the outer compensation capacitors are reduced by a factor k2and k, respectively. The proposed compensation technique was applied to a three-stage operational amplifier used to implement a voltage regulator: simulations of the regulator showed a significant improvement of slew rate, settling time, and transient output voltage drop when a load current is suddenly requested.

In this paper, an enhanced current pulse generator featuring fast transient response is presented. The proposed circuit offers the possibility to control specific design parameters to obtain the desired performance in terms of pulse shape, amplitude, input-output delay, and power consumption optimization under different load conditions. A detailed analysis of the enhanced current pulse generator that focuses on the improvements provided with respect to a standard solution is provided in the paper. The system has been integrated on a test vehicle in 110-nm BCD technology as part of the programming circuitry of a phase-change memory. Experimental results demonstrate the effectiveness of the proposed solution, which ensures a 300% faster transient response to reach 80% of the output-current amplitude with respect to a standard circuit.

A new architecture of charge-pump circuit is discussed that can be used to generate high positive and negative voltages to drive a common load (Load can be capacitive, resistive or both). Basic cell used for charge-pump consists of two phase clock signals, charge transfer NMOS transistors and bootstrapped configuration to boost the gate drive of NMOS transistors. Due to use of NMOS transistors, output resistance of circuit is lower than conventional circuits thus able to drive high load current. Electrical conditions of all devices used in the circuit is managed in such a way that there is no electrical stress across any transistor. Circuit is design and implemented in BCD-110nm technology using conventional (No DMOS) transistors.

A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets image-voice processing and recognition applications. Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. The system is implemented in a 0.18um, 2PL-6ML CMOS Flash technology, chip area is 70mm2.