All cultures and nations have long recognized that creativity is the ultimate cause of the quantum leaps in virtually every discipline of knowledge and the quiet and invisible force behind all progress of human civilization. Leading thinkers across all disciplines have advocated the importance of creativity and consistently ranked it well beyond intelligence. In the recent literature, creativity has been clarified as a phenomenon that categorically differs from intelligence in that the ideas that result from it may not be deduced by applying current reasoning techniques on the state-of-the-art knowledge. Thus, creativity transcends intelligence. Throughout history, close examination reveals that deep sadness and profound grief have always been associated with every creative activity and every individual engaged in a creative invention or discovery. This paper pioneers the analytical examination of a key question, namely, is the apparent association between creativity and sadness mere coincidence or does there exist a scientific reasoning, arising from a deep and fundamental connection between the two concepts? The potential benefits of this exercise, if successful, are two-fold. First, it encapsulates a systematic attempt to resolve a deep intellectual curiosity that has intrigued society for millennia. Second, as a practical benefit, a careful understanding of the theory of the underlying processes may help us analyze how best to nurture the course of any given creative activity and limit the grief or sadness so it does not spin out of control and consume the individual, denying civilization, today and for the future, the enormous benefits that may follow from the inventions and discoveries. It is an undeniable fact that sadness may affect every individual, at one time or another and this paper does not focus on assessing whether sadness is a prelude to a creative invention or discovery. Instead, its objective is to examine whether creativity, by nature, triggers a counter-posing force that leads to profound grief; or whether creativity and sadness are so intimately intertwined in their seat in human beings that evoking creativity automatically triggers intense grief

Current literature on input buffer management reveals that, in representative ATM networks under highly bursty traffic conditions, the fuzzy thresholding approach yields lower cell loss rate at the cost of lower throughput. Also, under less bursty traffic, the traditional fixed thresholding approach achieves higher throughput at the expense of higher cell loss rate. The translation of this finding into practice, termed adaptive dynamic input buffer management (ADBM), is the objective of this paper. The argument is that, given that the traffic conditions are constantly changing, to achieve efficiency during actual operation, the network control must dynamically switch, at every ATM switch, under the call processor's control, between the two input buffer management techniques, dictated by the nature of the traffic at the inputs of the corresponding switch. In order to best characterize the nature of the incoming traffic, the ADBM technique relies on the use of a counter and a choice of a time interval. The counter best determines the burstiness nature of the input traffic by counting the number of cells that are intercepted at the input of the switch over a defined time interval. The challenge posed by this proposition lies in the very definition of burstiness in that the time interval must approach, in the limit, zero or the resolution of time in the network. To address this challenge, a 15-node representative ATM network is modeled in an asynchronous, distributed simulator and, simulated on a network of workstations under realistic traffic stimuli. Burstiness indices are measured for the synthetic, stochastic traffic at the inputs of every ATM switch as a function of the progress of simulation for different choices of time interval values. Simulation results reveal superior performance for ADBM, with a throughput of 74.77% that is higher than even the pure fixed scheme, and cell drop rate of 2.21% that is lower than that of the pure fuzzy scheme. In essence, ADBM successfully integrates the best characteristics of the fuzzy and fixed thresholding schemes.

A principal attraction of ATM networks is that the key QoS parameters of every call are guaranteed by the network when appropriate cell-level traffic controls are imposed at the user network interface (UNI) on a per call basis, utilizing the peak cell rate (PCR) and sustainable cell rate (SCR) values for the traffic sources. The issue of providing QoS guarantees in the real world, through traffic controls applied on a per call basis, is rendered uncertain. This paper adopts a radically different, high level approach to the issue of QoS guarantees. It aims at uncovering through systematic experimentation a relationship, if any exists, between the key high level user traffic characteristics and the resulting QoS measures in a realistic operational environment. Based on the observation that the network provider cares for two factors, namely, to maximize the link utilization and to ensure the QoS guarantees for every user traffic, this paper proposes a two-phase strategy. Under the first phase, the average "link utilization" computed over all the links in a network is maintained within a range, specified by the underlying network provider, through high level call admission control, i.e. by limiting the volume of the incident traffic on the network, at any time. The second phase is based on the hypothesis that the number of traffic sources, their nature-audio, video, or data, and the bandwidth distribution of the source traffic, admitted subject to a specific chosen value of "link utilization" in the network, will exert a unique influence on the cumulative delay distribution at the buffers of the representative nodes and, hence, on the QoS guarantees of each call. Extensive simulations reveal that, for a given link utilization level held uniform throughout the network, while the QoS metrics are superior in the presence of many calls each with low bandwidth requirement, they are significantly worse when the network carries fewer calls of very high bandwidths. The findings demonstrate the feasibility of guaranteeing QoS for each and every call through high level traffic controls. The findings also underscore two additional important contributions of this paper. First, the network provider may guide and maintain the network at a desired network operating point (NOP) by exercising control over the input and system parameters including link utilization, call admittance etc. Second, the finding constitutes a vulnerability of ATM networks which a perpetrator may exploit to launch a performance attack.

This paper presents a new routing strategy, termed incremental virtual circuit connection (IVCC), that is ideally suited for a class of call requests that promise to underlie future high-speed networks. IVCC aims to reduce the idling of reserved resources, thereby improving the sharing of network resources among users and increasing call success rate. Under IVCC, the subsequent subpaths, starting at the source node, are computed, reserved, and utilized incrementally. Initially, the source node (SN) computes the entire path all the way to the destination node (DN), but propagates the call admission control (CAC) to reserve network resources only for a subset of the entire path, where the choice of the subpath is based on the organization and topology of the network. This paper hypothesizes that the efficient use of resources in IVCC will significantly reduce the probability of failures. Thus, IVCC's uniqueness consists of two key elements. First, the actual route for a source traffic is successively and dynamically refined, utilizing up-to-date information on the state of the network, but always keeping an "eye" towards the destination. Second, traffic cells are launched from the source node or any of the intermediate nodes only after the network resources along the subsequent subpath have been reserved. IVCC has been modeled for two representative ATM networks, a 15-node network spread over the continental US and a 50-node network extending throughout the world, and extensively simulated for a large number of realistic input traffic stimuli utilizing an asynchronous distributed simulation algorithm running on a network of workstations. For a comparative analysis, ATM Forum's P-NNI is also modeled and simulated for identical networks and under identical traffic conditions.

Given a process whose output is a dynamic function of time, the traditional discrete event specification (DEVS) approximates the input, output, and state trajectories through piecewise constant segments, where the segments correspond to discrete time intervals that are not necessarily equal in length. For processes that defy accurate modeling through piecewise constant segments, this paper presents GDEVS, a generalized discrete event specification, wherein the trajectories are organized through piecewise polynomial segments. The utilization of arbitrary polynomial functions for segments promises higher accuracies in modeling continuous processes as discrete event abstractions. In general, discrete event systems including DEVS and GDEVS execute faster on host computers because executions occur corresponding to significant changes in the system unlike in continuous simulations where execution is on a continuous basis. GDEVS' superiority over DEVS lies in its ability to discretize a system characteristic. A key contribution of GDEVS is that it permits the development of a uniform simulation environment for hybrid, i.e. both continuous and discrete, systems. GDEVS is illustrated for a first order system and a hybrid system, with piecewise linear segments. Two representative systems have been modeled under GDEVS and executed on a simulator developed for GDEVS.

The objective is to scientifically study the nature of creativity by modeling synthetic creativity in an ant colony, simulating it on a computer system, and measuring its impact on performance through innovative metric design. In this study, two synthetic creative traits are introduced into select individual ants of a colony by imparting to them a foraging behavior that is radically different from the normal behavior. Analysis of the simulation results reveal that a creative trait coupled with the underlying parameters of the ant colony may cause the foraging completion time metric, i.e. the time to collect food from all sources, to be marginally better or weaker than the normal colony. Contrary to intuition, the completion time metric worsens when, in a fixed sized colony, the number of creative ants, relative to normal ants, becomes excessive.

The DoD's very high speed integrated circuit Hardware Description Language, VHDL, is aimed at allowing hardware designers to accurately describe, simulate, and validate combinational and sequential hardware designs on computers prior to building a prototype. Since its conception in the early 1980s, an important goal of VHDL has been to execute complex models concurrently and efficiently on parallel processors. To achieve this objective while exploiting the maximum theoretical parallelism, one requires a deadlock-free, asynchronous, distributed, discrete event simulation algorithm. The YADDES approach, proposed in the literature, achieves deadlock-free, distributed, discrete event simulation, but suffers from an important limitation. YADDES assumes that every entity is characterized by a single propagation delay. In contrast, for hardware entities such as gates, flip-flops, ALUs, and microprocessors, two or more propagation delay values are used corresponding to every path between the input and output. While the use of multiple delays aims at accurate representation of reality, often inconsistent events may be generated that must be detected and preempted. This paper describes a new asynchronous, parallel, event driven simulation algorithm with inconsistent event preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in that it permits the use of any number of propagation delays for every path between the input and output of every hardware entity.

This paper addresses three key issues in buffer management in cell switching networks including asynchronous transfer mode (ATM) networks. First, it develops a model of fuzzy thresholding-based buffer management for a 50-switch representative cell-switching network, to study its performance under realistic conditions. Second, it presents an approach to re-route to their final destinations, the fraction of the selectively blocked cells that correspond to the difference of cell loss due to buffer overflow between the fixed and fuzzy schemes. Third, it reports on the influence of the buffer management scheme on the end-to-end delay performance of a representative cell switching network. The model is simulated on a testbed consisting of a network of 25+ Pentium workstations under Linux, configured as a loosely coupled parallel processor. Simulation results obtained are discussed.

Asynchronous distributed decision-making (ADDM) systems constitute a special class of distributed problems and are characterized as large, complex systems wherein the principal elements are the geographically dispersed entities that communicate among themselves, asynchronously, through message passing and are permitted autonomy in local decision making. Such systems generally offer significant advantages over the traditional, centralized algorithms in the form of concurrency, scalability, high throughput, efficiency, low vulnerability to catastrophic failures, and robustness. A fundamental property of ADDM systems is stability that refers to their behavior under representative perturbations to their operating environments, given that such systems are intended to be real, complex, and to some extent, mission-critical, and are subject to unexpected changes in their operating conditions. This paper introduces the concept of stability in ADDM systems and proposes an intuitive yet practical and usable definition that is inspired by those used in control systems and physics. An ADDM system is defined as a stable system if it returns to a steady state in finite time, following perturbation, provided that it is initiated in a steady state. Equilibrium or steady state is defined through placing bounds on the measured error in the system. Where the final steady state is equivalent to the initial one, a system is referred to as strongly stable. If the final steady state is potentially worse then the initial one, a system is deemed marginally stable. When a system fails to return to steady state following the perturbation, it is unstable. The perturbations are classified as either changes in the input pattern or changes in one or more environmental characteristics of the system, such as hardware failures. For a given ADDM system, the definitions are based on the performance indices that must be judiciously identified by the system architect and are likely to be unique. To facilitate the understanding of stability in representative real-world systems, this paper reports the analysis of two basic manifestations of ADDM systems that have been reported in the literature: (1) a decentralized military command and control problem, MFAD and (2) a novel distributed algorithm with soft reservation for efficient scheduling and congestion mitigation in railway networks, RYNSORD. Stability analysis of MFAD and RYNSORD yields key stable and unstable conditions. A system determined to be stable provides the reassurance that the system will perform well under adverse conditions. In contrast, a system deemed unstable reflects the need to address key weaknesses in the system design. Thus, stability analysis is a necessary and critical step in the development of any ADDM system.

For many military and civilian large-scale, real-world systems of interest, data are first acquired asynchronously, i.e., at irregular intervals of time, at geographically-dispersed sites, processed utilizing decision-making algorithms, and the processed data then disseminated to other appropriate sites. The term real-world refers to systems under computer control that relate to everyday life and are beneficial to the society in the large. The traditional approach to such problems consists of designing a central entity which collects all data, executes a decision-making algorithm sequentially to yield the decisions, and propagates the decisions to the respective sites. Centralized decision-making algorithms are slow and highly vulnerable to natural and artificial catastrophes. Recent literature includes successful asynchronous, distributed, decision-making algorithm designs wherein the local decision making at every site replaces the centralized decision making to achieve faster response, higher reliability, and greater accuracy of the decisions. Two key issues include (1) the lack of an approach to synthesize asynchronous, distributed, decision-making algorithms, for any given problem, and (2) the absence of a comparative analysis of the quality of their decisions. This paper proposes MFAD, a Mathematical Framework for Asynchronous, Distributed Systems, that permits the description of centralized decision-making algorithms and facilities the synthesis of distributed decision-making algorithms. MFAD is based on the Kohn-Nerode distributed hybrid control paradigm.

For many military and civilian large-scale, real-world systems of interest, data are first acquired asynchronously, i.e. at irregular intervals of time, at geographically-dispersed sites, processed utilizing decision-making algorithms, and the processed data then disseminated to other appropriate sites. The term real-world refers to systems under computer control that relate to everyday life and are beneficial to the society in the large. The traditional approach to such problems consists of designing a central entity which collects all data, executes a decision making algorithm sequentially to yield the decisions, and propagates the decisions to the respective sites. Centralized decision making algorithms are slow and highly vulnerable to natural and artificial catastrophes. This paper proposes MFAD, a Mathematical Framework for Asynchronous, Distributed Systems, that permits the description of centralized decision-making algorithms and facilities the synthesis of distributed decision-making algorithms. MFAD is based on the Kohn-Nerode distributed hybrid control paradigm. It has been a belief that since the centralized control gathers every necessary data from all entities in the system and utilizes them to compute the decisions, the decisions may be "globally" optimal. In truth, however, as the frequency of the sensor data increases and the environment gets larger, dynamic, and more complex, the decisions are called into question.

The use of fuzzy logic in telecommunication systems and networks is recent and limited. Fundamentally, Zadeh's fuzzy set theory provides a robust mathematical framework for dealing with "real-world" imprecision and nonstatistical uncertainty. Given that the present day complex networks are dynamic, that there is great uncertainty associated with the input traffic and other environmental parameters, that they are subject to unexpected overloads, failures and perturbations, and that they defy accurate analytical modeling, fuzzy logic appears to be a promising approach to address many important aspects of networks. This paper reviews the current research efforts in fuzzy logic-based approaches to queuing, buffer management, distributed access control, load management, routing, call acceptance, policing, congestion mitigation, bandwidth allocation, channel assignment, network management, and quantitative performance evaluation in networks. The review underscores the future potential and promise of fuzzy logic in networks. The paper then presents a list of key research efforts in the areas of fuzzy logic-based algorithms and new hardware and software architectures that are necessary both to address new challenges in networking and to help realize the full potential of fuzzy logic in networks.

The ability to accurately represent and execute the timing behavior of digital hardware constitutes a fundamental characteristic of any hardware description language including ADLIB-SABLE and the US DoD's VHDL. Unlike its predecessor hardware description languages that utilized a single delay construct, the VHDL grammar proposes two syntactic constructs-inertial and transport delays, and the VHDL language defines their semantics to facilitate accurate modeling of the timing behavior. Inertial delays are utilized to model the timing behavior of digital components such as gates and flip-flops where a new input signal must persist for a minimum specified duration so as to initiate a change in the state of the component. Transport delays, on the other hand, are designed to model devices with infinite frequency response, i.e., where any new input signal, regardless of its duration, will initiate a change in the state of the component. Examples of such devices include bus and clock interconnect lines. The design of transport delay suffers from two major flaws. First, there is an implicit assumption that in an interconnect with multiple taps, only one tap is a driver, and the signal reaches the other taps delayed only by the time necessary for the electromagnetic propagation. Thus, the perturbation due to reflection at the intermediate taps is ignored, and this results in incorrect timing behavior. Second, for today's increasing higher clock speeds and newer bus design techniques such as Intel's PCI, the corresponding clock time period increasingly compares with the delay along the interconnects. Thus, interconnects increasingly behave like transmission lines, and accurate modeling warrants the use of transmission line analysis. This paper proposes new additions to the existing VHDL grammar, and defines new semantics in the language to accurately model the timing behavior of high-frequency buses and clock lines with multiple, distinct taps. The proposed language constructs utilize transmission-line analysis to model the timing behavior of "long" lines. A long line is characterized by the inequality {t/sub r//T/sub prop//spl les/2}, where t/sub r/ and T/sub prop/ represent the finite signal transition time for the wave and the propagation delay of the wave from the driver to the load, respectively. True transmission line analysis, however, requires analog simulation that is accurate, yet painfully slow. Also, analog simulation is incompatible with the event-driven simulation algorithm that constitutes the basis of execution of hardware description languages. This paper develops an algorithm that is based on the underlying transmission-line analysis, but is event driven and computationally fast. It computes the state of incident, reflected, and refracted (or transmitted) waves at each of the distinct, discrete taps along the bus, thereby generating accurate timing behavior. This paper also presents the design of a simulator that implements the proposed timing construct. A number of experiments are conducted wherein an Ethernet bus, under "collision" and "no-collision" scenarios, a TTL wired-OR bus under single driver and wired-OR glitch scenarios, and the new Intel PCI bus are modeled and executed on the simulator. Performance analysis reveals that while the simulation results accurately match the actual behavior of buses, the simulation executes fast.

The concept of continuity in medicine is fundamental and it refers to the delivery of medical care to a patient by a care provider in an uninterrupted and coordinated manner and in accordance with the medical care needs of the patient. Principal limitations of previous studies include the following. First, there is the absence of a deliberate effort to schedule a patient's successive visits with the same provider. Second, in most cases, the reported measures are derived from the data collected through questionnaires that patients and doctors are asked to complete from memory. This introduces an unreliability factor. Third, the reported continuity-related measures are restricted to the available patient sample and, as a result, they do not necessarily reflect a representative patient distribution by age in a typical community. Fourth, the relationship between the patient-doctor interaction interval and the continuity of medical care has never been explored systematically in the literature. This paper models continuity for a representative staff model health maintenance organization (HMO) clinic in suburban Arizona and simulates patient visits that are stochastically generated through utilizing representative numbers of patient visits and care providers. It focuses on individual-based continuity delivered by a primary care provider, i.e., a general practitioner. In the simulation, the visit patterns of patients, their ages, and the length of the interaction episodes are synthesized stochastically. The distributions reflect both the patient visit profile, by age, inherent in the 90,000+ patient electronic records collected at the CIGNA HMO clinic at Chandler, AZ, over a three-year period, and the population distribution inherent in the CIGNA records. A key characteristic of the model is that it aims at deliberately maximizing continuity by making a strong effort to schedule both a patient's regular visit and follow-ups with the primary care provider, subject to the provider's availability and schedule. This paper proposes a new definition of continuity, fundamental continuity of care index (FCCI), and argues that, fundamentally, a primary care provider's depth of understanding of the patient is directly proportional to the total length of interaction between the patient and the primary care provider. Utilizing the CIGNA summary data, this paper organizes patients into five age groups: 0-5 years, 5-15 years, 15-45 years, 45-60 years, and 60+ and synthesizes the corresponding arrival distributions. Performance results, obtained for a total of 55,056 patient visits over a three-year period indicate that, while 94-97% of the patient visits are with the primary care provider, patients spend 76-77% of the nominal total visit time with their primary care provider, leading to FCCI values ranging from 0.72 to 0.75. Performance results indicate that for different choices of the mean of the patient-doctor interaction duration, the average FCCI values, obtained following simulation, reveal an approximate bell-shaped graph. For values of the mean ranging from 5 to 10, 15, 20, 25, 35, 45, and 55 min, the average FCCI measure starts at 0.49, increases to a maximum of 0.88 corresponding to a mean of 25 min, and then decreases to 0.60. Thus, for a medical clinic, constrained by the number of care providers servicing a fixed number of patients, for a given population distribution by age, an optimum value for the average patient-doctor interaction duration may be obtained empirically that yields the maximal continuity measure.

The design of VHDL transport delay uses an implicit assumption that bus with multiple taps, only one tap is a driver and the signal reaches the other taps delayed only by the time necessary for the electro-magnetic propagation. Perturbation due to reflection at the intermediate taps, is ignored and this results in incorrect timing behavior. This paper proposes extensions to VHDL grammar and defines new semantics in the language to accurately capture and model the transport timing behavior of buses with multiple, distinct taps.

The discipline of discrete event simulation may be utilized to model many physical systems such as digital hardware, queueing networks, telephone networks, simulated warfare, and banking transactions. Where the entities of a physical system execute independently and interact asynchronously, an asynchronous distributed event-driven simulation algorithm may enable the simulation of the system to execute on a parallel processor. This has the potential to significantly reduce the total simulation time. YADDES is the first algorithm that is characterized by: (1) acceptable performance, (2) freedom from deadlock, and (3) probably correct, for circuits where the interactions between the entities constitute a cyclic dependence. Given their complex, asynchronous nature, an important issue associated with all asynchronous distributed algorithms is their correctness, i.e., the generation of accurate output for given input stimulus, under all possible conditions. This paper presents a mathematical proof of correctness and reports the performance of YADDES on the Armstrong parallel processor at Brown University.

Article Free Access Share on Asynchronous, distributed event driven simulation algorithm for execution of VHDL on parallel processors Authors: Peter A. Walker Division of Engineering, Brown University, Providence, Rhode Island Division of Engineering, Brown University, Providence, Rhode IslandView Profile , Sumit Ghosh Division of Engineering, Brown University, Providence, Rhode Island Division of Engineering, Brown University, Providence, Rhode IslandView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 144–150https://doi.org/10.1145/217474.217521Published:01 January 1995Publication History 5citation287DownloadsMetricsTotal Citations5Total Downloads287Last 12 Months14Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In a radical shift from the previous doctrine of firepower, attrition, and destruction during the Vietnam era, the current "airland battle" military doctrine is characterized by four key ingredients -- depth, initiative, agility, and synchronization. The term, synchronization, implies bringing to bear, at one time and place, the combined power of maneuver, artillery, air, deception, and other systems so as to strike the enemy again and again with an impact that exceeds the sum of all the parts. Throughout military history, in general, synchronization has been achieved through centralized command, control, and communication (C 3 ), i.e. one where all intelligence is collected and decisions generated at a centralized, sequentially executing entity. While the military synchronization is laid down by a higher command and must be obeyed, the lower level units are granted military initiative as to how to achieve the requirements of synchronization. However, at any given level in the milita...

Traditional approaches to the distributed simulation of digital designs are limited in that they are inefficient and prone to deadlock for systems with feedback loops. This paper proposes an asynchronous distributed algorithm to the simulation and verification of behavior-level models and describes its implementation on an actual loosely-coupled parallel processor. The approach is relatively efficient for realistic digital designs and mathematically shown to be deadlock free. Additionally, it includes a new technique for modeling the timing of digital systems that guarantees the accuracy of the simulation results. In the discipline of computer-aided design of digital systems, a behavior model refers to a compact and executable representation of the activities of a complex digital component or an entire digital system such as the Motorola 68000, expressed through a high-level hardware description language such as ADLIB or VHDL. Behavior models are popular because of their flexibility; however, they execute excruciatingly slow on uniprocessor computers. The approach presented in this paper has the potential to significantly reduce the execution time through concurrent execution on multiple processors.>

PRISM, a computer architecture consisting of a general-purpose core processor and a reconfigurable FPGA platform, was designed to bridge the gap between general-purpose and specialized computers. PRISM-I, introduced a new concept wherein a custom architecture, utilizing the FPGAs, is dynamically and automatically created to execute a specific C program more efficiently. Speedup is achieved by executing frequently executed functions of the program on the custom-synthesized hardware while the remainder of the program executes on the core processor. PRISM-I, however, being a proof-of-concept system, suffers from several limitations, principal among them being that the evaluation time of a function is restricted to a single bus-cycle, loops with variable iteration counts are not allowed in the function, and control constructs, i.e. "if-then-else," are not executed efficiently. This article introduces a significant conceptual advancement, PRISM-II, that synthesizes asynchronous, adaptive architectures for C programs and addresses the above limitations of PRISM-I in a general manner. PRISM-II introduces a novel execution model and a framework for translating a C function into an FPGA-based custom architecture.

The paper introduces a novel architecture for asynchronous, hierarchical, international, geographically distributed, real-time banking, NOVAHID. NOVAHID is organized as a hierarchical approach. The paper assumes that nations may be organized into unique and autonomous entities, termed groups. The lower level of the hierarchy consists of discrete "group-networks" where each group-network is synthesized from the Equivalent Federal Reserve banking nodes of the nations served by the group-network. At the highest level of the hierarchy, representative entities of the groups are interconnected through a "top-level-network". The hierarchy reflects the underlying assumption that a significant fraction of all transactions is local to the group-networks. NOVAHID utilizes the principles of YADDES, which embodies the principle of an asynchronous, discrete-event simulation algorithm for cyclic circuits and mathematically guarantees the accuracy of the execution of events. Each banking transaction is modeled as an event in discrete-event simulation. NOVAHID guarantees the accuracy of every transaction and, hence, the accurate balance of every account at all times. NOVAHID offers to any user the banking privileges of withdrawal, deposit, and transfer anywhere and at any time in the world. The paper also describes a model and implementation of NOVAHID on a loosely coupled parallel processor. Performance measures are also reported.>

High-performance cell-based communications networks have been conceived to carry asynchronous traffic sources and support a continuum of transport rates ranging from low bit-rate to high bit-rate traffic. When a number of bursty traffic sources add cells, the network is inevitably subject to congestion. Traditional approaches to congestion management include admission control algorithms, smoothing functions, and the use of finite-sized buffers with queue management techniques. Most queue management schemes, reported in the literature, utilize "fixed" thresholds to determine when to permit or refuse entry of cells into the buffer. The aim is to achieve a desired tradeoff between the number of cells carried through the network, propagation delays of the cells, and the number of discarded cells. While binary thresholds are excessively restrictive, the rationale underlying the use of a large number of priorities appears to be ad hoc, unnatural, and unclear. The paper introduces the notion of cell-blocking, wherein a fuzzy thresholding function, based on Zadeh's (1965) fuzzy set theory, is utilized to deliberately refuse entry to a fraction of incoming cells from other switches. The blocked cells must be rerouted by the sending switch to other switches and, in the process, they may incur delays. The fraction of blocked cells is a continuous function of the current buffer occupancy level unlike the abrupt. The fuzzy cell-blocking scheme is simulated on a computer. Fuzzy queue management adapts superbly to sharp changes in cell arrival rates and maximum burstiness of bursty traffic sources.>

The issue of monitoring the execution of asynchronous, distributed algorithms on loosely-coupled parallel processor systems, is important for the purposes of (i) detecting inconsistencies and flaws in the algorithm, (ii) obtaining important performance parameters for the algorithm, and (iii) developing a conceptual understanding of the algorithm's behavior, for given input stimulus, through visualization. For a particular class of asynchronous distributed algorithms that may be characterized by independent and concurrent entities that execute asynchronously on multiple processors and interact with one another through explicit messages, the following reasoning applies. Information about the flow of messages and the activity of the processors may contribute significantly towards the conceptual understanding of the algorithm's behavior and the functional correctness of the implementation. The computation and subsequent display of important parameters, based upon the execution of the algorithm, is an important objective of DIVIDE. For instance, the mean and standard deviation values for the propagation delay of ATM cells between any two given Broadband-ISDN (BISDN) nodes in a simulation of BISDN network under stochastic input stimulus, as a function of time, are important clues to the degree of congestion in the Broadband-ISDN network. Although the execution of the algorithm typically generates high resolution data, often, a coarse-level visual representation of the data may be useful in facilitating the conceptual understanding of the behavior of the algorithm. DIVIDE permits a user to specify a resolution less than that of the data from the execution of the algorithm, which is then utilized to coalesce the data appropriately. Given that this process requires significant computational power, for efficiency, DIVIDE distributes the overall task of visual display into a number of user specified workstations that are configured as a loosely-coupled parallel processor. DIVIDE has been implemented on a heterogeneous network of SUN sparc 1 + , sparc 2, and 3/60 workstations and performance measurements indicate significant improvement over that of a uniprocessor-based visual display.>

The payment-processing system in the banking industry consists of deposits, withdrawals, and transfers of monies through the use of cash, checks, magnetic tapes, and electronic transactions. Most transactions are realized by batch-mode processing. Batch-mode processing suffers from many limitations, the principal ones being that 1) users are denied real-time access to their money and that 2) a user's banking privileges cannot be extended anywhere in the USA-a facility that is increasingly being demanded by users. It is observed that the banking process may be mathematically mapped to a discrete-event simulation system with feedback loops wherein deposits, withdrawals, and transfers may be modeled as events that are introduced into the system asynchronously, i.e. at irregular intervals of time. A new architecture, NOVADIB, is proposed for the check processing subsystem of the Federal Reserve System that distributes the processing operations to multiple, concurrent, cooperating geographically distributed computers, i.e. at many sites, to achieve real-time transaction processing. NOVADIB utilizes the principles of asynchronous, distributed, discrete-event simulation algorithm for cyclic circuits, YADDES, and mathematically guarantees the accuracy of every transaction.>

The authors examine the limitations of the timing semantics in the conventional behavioral simulators and present a preemptive scheduling mechanism for accurate behavioral simulation results. They consider two signal transitions at the input ports of a component, where the second input transition arrives later than the first transition. The first and second input transitions cause first output signal transitions O/sub 1/ and O/sub 2/, respectively, to be generated at the output port of the component. When the logical values of O/sub 1/ and O/sub 2/ conflict with each other and O/sub 1/ arrives later than O/sub 2/, O/sub 1/ is preempted by O/sub 2/. In addition, an input signal to a component whose pulse duration is smaller than the inertial delay of the component, T/sub mip/, is discarded during simulation. Empirical measures for T/sub mip/ relative to the high-to-low and low-to-high propagation delays of the component for TL (transistor-transistor logic), NMOS, and CMOS technologies are presented. This approach has been implemented in the ADLIB-SABLE simulator at Stanford University.>

A mechanism is presented to represent failures in complex combinational digital and VLSI designs at a high level, referred to as behavior fault models. The advantages of behavior fault modeling include early estimates of reliability of the design in the design process, reduced CPU time for fault simulation, and results that may be more comprehensive to the high-level architects. Digital and VLSI components are expressed in a high-level hardware description language and the fault models proposed are based on the failure modes of the language constructs of a generic hardware-description language. Evaluation of such fault models is also reported through a correlation of the behavior fault simulation results of representative example designs with fault simulation of equivalent gate-level representations in the presence of stuck-at faults.>

A new approach to the timing verification of digital designs is introduced in this paper. The approach is capable of verifying synchronous and asynchronous digital designs including self-timed asynchronous circuits [10]. Every component in a circuit is represented by a timing description that may concurrently execute with other descriptions. Communication between and scheduling of the timing descriptions are distributed in every description and, in this approach, parallelism may be utilized with relative ease. Conventional approaches to timing verification such as SCALD [7], TV [5], and the one reported by Hitchcock [4] are limited to the verification of synchronous designs only. The approach has been verified through an implementation in the RDV system [3] at Stanford University. Descriptions of timing models of asynchronous and synchronous digital devices including a simplified AMD2903 architecture are also presented in this paper.

A novel approach to design verification is presented that is based on a new methodology for modeling and verifying digital designs. The verification methodology unifies functional and fault simulation and timing verification into one general rule-based framework wherein functional, fault, and timing characteristics of digital designs are expressed through a set of rules. Consequently, models of new devices and for new types of simulations may be introduced into the verification system with relative ease. Introducing other types of simulations into the verifier would require expressing the appropriate characteristics of digital devices in the form of rules. This approach has been verified in the experimental RDV [GS84] system at Stanford University and the hardware-description language used is Ada [AD83]. Unification of functional and fault simulation and timing verification is made possible by a combination of distributed approaches to modeling and scheduling.