In this IP session, there will be 3 presentations focusing on the state-of-the-art memory test practices from tools and industrial implementation perspectives. The 1stpresentation will discuss the memory test strategies in the automotive space. The 2ndpresentation discusses memory tests strategies for enabling test cost reduction. The 3rdpresentation will discuss on array BIST and its presence and usage in various applications of the current generation designs.

Low-power testing has become a need for modern designs due to rapid increasing of power density with further shrinking of feature size into nanoscale designs. In spite of low-power design efforts and low-power ATPG adopted in common test flows, excessive power dissipation and instant peak current cannot be necessarily avoided during test application. There is a need for fast peak power detection for test vectors. The test industry lacks such efficient solution. In this work, we propose a fast test power analysis methodology. By reading and processing layout data and other supporting files such as parasitic files, the proposed analysis engine performs a simplified power grid analysis with layout partition and provides following power results for each test cycle: switching activity, absolute power, hot spot contour map, absolute current estimation on power pads. The proposed flow was verified on industry designs and proved to be very efficient than using commercial power sign-off solutions for test power analysis.

Use of Nand Flash memory in storage devices is increasing at an exponential rate. As the technology feature size shrink, the reliability and endurance for the Nand device reduces. Currently Nand devices can have more than 258Gb cells. Testing such devices is not a trivial proposition. In this presentation we will discuss the failure modes for Nand flash, the test methods used and the challenges that we face.

Diagnosing failing vectors in a Built-Zn Self Test (BZST) environment is a dificult task because of the highly compressed signature coming out of the Multiple Input Shift Register (MISR). The root cause of the failure must be initially narrowed down to the failing vectors and also the scan cells at which mismatches occurred. In this work, we propose a method for accurately determining the first cycle at which incorrect responses were captured in the scan chains along with the scan cells that captured the incorrect responses. We define a diagnosis methodology that describes a simple way of diagnosing one chain at a time and jLrther shows that accurate diagnosis is possible with the aliasing nature of the MISR having no impact on diagnosis. The proposed technique results in identibing the failing vectors along with the mismatching scan cells. After determining the failing vectors and mismatching scan cells, we extend the method to identifj, potential faults in the circuit that may have resulted in the scan cells capturing incorrect responses. The method presented in this paper can be applied to diagnose multiple failing vectors also.

Work in path delay fault testing and fault simulation has gained importance in the industry since supplementing stuck-at fault coverage with delay fault coverage may result in better defect coverage than that is possible with stuck-at fault coverage alone. Timing related failures must be diagnosed to determine which nodes or paths in the circuit have excessive delays and techniques are needed to simplify the process of attributing the delays to a minimal set of nodes or paths. In this work, we propose a method for determining path delay faults that are tested simultaneously by the same test and do not have separate tests either because of circuit functionality or restrictions imposed by a given test set. We call such faults indistinguishable path delay faults. We further propose a method for identifying scanout nodes in the circuit that reduce the number of indistinguishable faults and improve diagnostic resolution. The method for identifying indistinguishable faults can be used before test application to determine the extent of diagnostic resolution possible for a given test set. It also enables a designer to make the design changes needed for improving diagnostic resolution. This has a large impact on the turnaround time for the diagnosis and debug processes. We perform experiments on the partitions of a picoJava/spl trade/ processor core to show the effectiveness of the proposed method. Results show that it requires only a reasonable amount of time for identifying indistinguishable faults and that the proposed methods are practical for deployment in an industrial environment.

Recent techniques for path delay fault diagnosis have addressed the problem in combinational circuits and sequential circuits. The root cause of a path delay fault test failure is narrowed down to a set of functionally sensitized paths and this set is further reduced by post processing the set of passing tests. In this paper, we present a method for narrowing down the suspects further to a set of segments on the failing functionally sensitized paths. The proposed method is implemented and applied to a set of industrial circuits and it is found to be very effective in determining the defective segments that explain excessive delays along paths.

This paper presents a method of primitive fault identification and test generation for combinational and nonscan sequential circuits. It uses the concept of sensitizing cubes to obtain input vectors that statically sensitize primitive faults in combinational circuits. The same technique is used to identify combinationally primitive faults in the next-state and output logic of sequential circuits. Such faults are primitive if and only if the fault effects on paths to state variable flip-flops can be propagated to a primary output (PO). Test sequences, including initializing sequences from a reset state and sequences that propagate fault effects from flip-flops to POs, are generated for primitive faults, wherever possible. The proposed method has been implemented and used to derive tests for primitive faults in the ISCAS'89 and MCNC'91 benchmark circuits. It was able to find all primitive faults and also obtain robust tests for a large fraction of them when the circuits were treated as combinational. When the same circuits were treated as nonscan sequential circuits, all primitive faults could not be found because fault propagation had to be limited to a relatively small number of time frames.

Path delay fault testing has been widely pursued in literature, primarily because of the need for determining the optimal speed of circuit operation. The existing techniques for path delay fault diagnosis are oriented towards determining the delay defects based on a given test set. In this paper, we propose a method for modifying a given test set such that the resultant test set is more effective in determining paths with excessive delays. The process of modifying the given test set is built upon an accurate algorithm for identifying all the single and multiple faults static sensitized by a given test set. The tests are then ordered such that it becomes faster and easier to identify paths responsible for timing failures. The modified test set results in an overall improvement in test quality and better diagnosis. The proposed approach can be used before test application for modifying the test set and improving diagnosis. Experiments are performed on the ISCAS' 89 and MCNC' 91 benchmark circuits to show the effectiveness of the proposed method for path delay fault diagnosis.

A path delay fault in a sequential circuit will affect circuit timing only if it can be activated during normal operation of the circuit. Since vector pairs that can be applied to the next-state logic of a nonscan sequential circuit are restricted by the available state transitions, some faults may be impossible to activate. Such faults are redundant and need not be tested. In this paper, we present a method of identifying redundant path delay faults in the next-state logic implemented in a two-level sum of products form and extend it to multilevel realizations. Experimental results on MCNC'91 benchmarks show that large fractions of faults in most of the MCNC'91 benchmarks are redundant.

Recent research has characterized a class of faults, called primitive faults, that must be tested to insure timing correctness of digital circuits. Experimental results have shown that a large fraction of primitive faults usually have only non-robust tests. In this paper, we propose a method of improving robust coverage of primitive faults using test point insertion. An important feature of the proposed method is that instead of considering primitive faults explicitly, single faults are analyzed to determine whether they can be members of robustly testable primitive faults. If not, test points are specified to make any primitive fault containing such faults robustly testable. Results of experiments to determine the effectiveness of the proposed method show significant improvements in fault coverage.

A method is presented for identifying primitive path-delay faults in non-scan sequential cixuits and generating robwt tests for all robustly testable primitive faults.It uses the concept of sensitizing cubes introduced in an earlier paper and a nw, more eficient algon.thmforgenerating them.Sensitizing cubes of the natstate and output logic are used to obtain static sensitizing vectors that can be applied to the non-scan sequential cixuit as part of a vector-paiz These vector-pairs are also used in den.ving robust tests.Initializing sequencesfim a reset state and sequences that propagate fault effects~m @p-@ps to pn.nra~outputs are also generated The proposed method has been implemented and used to derive testsforprimitivefaults in ISCAS'89 and MCNC'91 benchmark cixuits.

The paper presents a method of identifying primitive path delay faults in combinational circuits, and deriving robust tests for all robustly testable primitive faults. It uses the concept of sensitizing cubes to reduce the search space. This approach helps identify faults that cannot be part of any primitive fault, and avoids attempting test generation for them. Sensitization conditions determined for primitive fault identification are also used in test generation, reducing test generation effort. Experimental results on some of the ISCAS'85 and MCNC'91 benchmark circuits indicate that they contain a fair number of primitive multiple path delay faults which must be tested.

The path delay fault testability of sequential circuits is limited by state transitions that can be produced during normal operation. As a result, there may be untestable faults some of which may affect circuit behavior. The authors first extend the concept of primitive faults to sequential circuits. They then describe a method of selecting a set of flip-flops for partial enhanced-scan, such that falling transitions on all paths are made robustly testable in a two-level prime and irredundant realization of the sequential circuit. It results in a robust or VNR test for every rising transition primitive fault, using the available state transitions. A method of synthesizing sequential circuits such that untestable faults do not affect the initialization, is presented. An area comparison between area-optimized and delay-verifiable versions of the MCNC '91 benchmark circuits is also presented.

Path delay fault testing in non-scan sequential circuits is complicated by the limited state transitions during normal operation. An accepted method for overcoming this difficulty is to use a scan chain consisting of enhanced scan flip-flops which makes the application of arbitrary vector pairs possible. However, the method results in increased path delays because of the enhanced scan flip-flops themselves. In this paper we present a new method for improving path delay fault testability without increasing path delays in the circuit. It uses a simple clock control circuit to produce single bit transitions on state variables and a parity check circuit for observing state variable flip-flops. The area overhead of this method is comparable to enhanced scan but no performance penalty is incurred. We demonstrate the effectiveness of this method in delay testing and show how it can be used for stuck-at fault testing.