Demo Data from EDBT 2026 / reviewers in the wild / expert
Shih-Yuang Su
dblp:00/1702
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 1 | 1994 | Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns · IEEE Trans. Computers 1994 |
Electronic design automation › hardware verification and test › combinational circuit testing
iterative logic array testing |
0.0 | 1 | 1994 | Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns · IEEE Trans. Computers 1994 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1994 | Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns · IEEE Trans. Computers 1994 |
Electronic design automation › hardware verification and test › testability improvement
c-testability |
0.0 | 1 | 1994 | Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns · IEEE Trans. Computers 1994 |
Methods — techniques the papers use, named apart from their topics
test vector generation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of PatternsabstractShows that a constant number of test vectors are sufficient for fully testing a k-dimensional ILA for sequential faults if the cell function is bijective. The authors then present an efficient algorithm to obtain such a test sequence. By extending the concept of C-testability and M-testability to sequential faults, the constant-length test sequence can be obtained. A pipelined array multiplier is shown to be C-testable with only 53 test vectors for exhaustively testing the sequential faults.> Shih-Yuang Su, Cheng-Wen Wu |
IEEE Trans. Computers | 1 |