Most of the existing techniques for palmprint recognition rely on metrics, typically based on static functions, which evaluate the distance between a pair of features. In this paper, we propose a new technique for palmprint verification based on a dynamical system approach for principal palm lines matching. The proposed dynamic algorithm is recursive and involves a positive linear dynamical system, whose evolution depends on the matching level between the two input images. In a preprocessing phase, the procedure iteratively erodes both of the images to be compared, by eliminating points in each image that do not have enough close neighboring points both in the image itself and the comparison image. As a result of the iterations, only the points that have enough neighboring points in both the image itself and in the comparison image can survive. Thus, the output of the dynamical system converges either to zero, when a deep mismatch exists between the two images, or to a high value, when a good matching is observed. The results, in terms of verification, are in line with the state-of-the-art results in the current literature. The main advantage of the approach is its robustness when dealing with low-resolution and noisy images. The impact of noise (e.g., salt and pepper noise) is effectively reduced: images corrupted with such noise are easily recognized, while a randomly generated image is rejected even when compared with itself.

Dynamic, large social events with concurrent activities, in which participants view, but also provide high-quality content to other visitors, pose one of many challenges to multimedia delivery. Distributing content in such a situation is difficult, and requires strong support from the underlying network, in order to quickly respond to changes in supply and demand. A Flock is a flexible overlay built in a self-organized, decentralized manner, relying on a simple interest-property concept. In this paper, we use Flocks to build large overlays that are both content- and Quality-of-Service (QoS) aware, and show how they adapt their structure dynamically, depending on interests in available QoS. We evaluate their performance under churn and large scale failures through extensive simulations, and practical experiments under Internet conditions on the Planet Lab, and present a selection of our results.

An enhancement to the CSMA p-persistent protocol family is proposed, based on a fully decentralized control that adjusts the message transmission rate of each node to the estimated density of surrounding transmitting nodes. The system does not require enumeration of nodes nor control messages, the only input to the control coming from the physical medium occupation. In addition to communication protocols, this technique can be used as inexpensive and efficient density estimation of physical entities in highly dynamic scenarios. Stability conditions are proposed by means of a rigorous theoretical investigation. We prove that our algorithm ensures stability even with unknown and time--varying network topologies. We show that good channel exploitation levels can be assured as well by suitably tuning the control parameters. A digital algorithm for practical implementation is proposed. The results are supported by simulation experiments.

Both simulation for design verification and fault simulation in conjunction with automatic test pattern generation (ATPG) would benefit from forward and backward shifting of the simulation time. Except in some particular cases, however this has so far been only allowed through explicit save/restore commands issued by the user. The paper presents a general technique that makes a "run for T" command possible, where T can be any positive or negative time value. A major feature is that the user can set she maximum allowable overhead. Its generality allows its implementation in simulators for design verification and fault simulators, for both synchronous and asynchronous circuits, with either zero-delay or accurate delay models.

Creator is a concurrent simulator for design verification and fault simulation of large circuits that highly integrates several traditional and innovative techniques. This is achieved by the introduction of a minimal information concept. Traditional techniques derived from previous works are Multiple List Traversal (MLT), trigger inhibition, fraternal event processing, list events, acid clock suppression, whereas the new ideas are function lists and evaluation functions, persistence time, positioning algorithm, evaluation triggering algorithm, combination of Single List Traversal (SLT) and MLT, and the implementation of transport delay in fault simulation. Generally the concurrent algorithm increases in complexity and the implementations grow in size and lose in performance as soon as higher abstraction levels are added beyond the gate one. To overcome this limitation, all the Creator's techniques are not related to a specific abstraction level and lead to an intrinsic multilevel concurrent fault simulator. Experimental results are reported to compare Creator with our previous simulator and the state-of-the-art commercial simulator Verifault-XL on several platforms.>

Both simulation for design verification and fault simulation in conjunction with automatic test pattern generation could take advantage of the possibility of moving the simulation time forward and backward. Up until now, rollback was allowed only by explicit backup/restore commands issued by the user. The paper presents a technique that makes possibles a "run for T" command, where T can be any time value, either positive or negative. It is based on an adaptive mechanism that automatically controls the parameters of an advanced network status recording system. A major feature is that the user may decide the maximum allowable overhead. Experiments show that the resulting rollback time is on the average very short, and therefore this technique can be efficiently used to improve sequential ATPG algorithms.>

Article Free Access Share on Creator: General and efficient multilevel concurrent fault simulation Authors: P. L. Montessoro CENS/CNR, Politecnico di Torino, Torino, Italy CENS/CNR, Politecnico di Torino, Torino, ItalyView Profile , S. Gai Dip. di Automatica ed Informatica, Politecnico di Torino, Torino, Italy Dip. di Automatica ed Informatica, Politecnico di Torino, Torino, ItalyView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 160–163https://doi.org/10.1145/127601.127653Online:01 June 1991Publication History 12citation157DownloadsMetricsTotal Citations12Total Downloads157Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Fault simulation is a heavy task, and large experiments may require several hours to complete. So far, therefore, fault simulation has been considered a batch task. In this paper some innovative design concepts for the user interface are presented, to provide easy and powerful control of the experiments. The Creator's user interface is an example of actual implementation. It can control one or more simulation experiments running on the same computer or on different machines in a computer network, and each simulation can be dynamically switched between interactive and batch mode. The system is based on a network communication tool, specially developed, and on the X-11 standard for the graphical features.>

Accuracy, generality and efficiency are critical factors when fault simulation of VLSI circuits is the target. The concurrent algorithm is the only solution when generality and accuracy is required. Its differential representation of the network status saves memory and CPU time, but due to its complexity the implementations grow in size and lose in performance as soon as higher abstraction levels are added beyond the gate one. In the paper the minimal information concept is discussed, and its applications to the key algorithms for concurrent event-driven simulation are shown. New advanced generalized techniques for multiple list traversal (MLT), trigger inhibition, fraternal event processing, list events, edge sensitive inputs, compile-driven evaluation functions, functional fault sources and clock suppression are presented for the first time in a truly unified context.>

The dynamic removal of faults before the end of the test pattern is reached, called fault dropping (FD), is considered. The conventional technique, called synchronous FD, is analyzed. An asynchronous FD method is introduced and its performance compared with that of the conventional method. It is based on the concept of removing descriptors while the simulation procedures access the data structure. This technique guarantees the maximum efficiency in reducing the computational effort. Experimental results show that it can considerably speed up simulation, particularly for large networks. It is shown that a mixed synchronous/asynchronous approach can optimize the total amount of memory needed.>

A technique, referred to as asynchronous fault dropping, is discussed. It is based on the concept of removing descriptors while the simulation procedures access the data structure. This technique guarantees the maximum efficiency in reducing the computational effort. Experimental results show that it can considerably speed up simulation, particularly for large networks. Lastly, consideration is given to the possibility of using a mixed approach in the light of the dynamic memory requirement during the initialization phase. It is shown that combination of synchronous and asynchronous fault dropping can optimize the total amount of memory needed.>

MOZART, a concurrent fault simulator for large circuits described at the register-transfer, functional, gate, and switch levels, is described. The requirements of multilevel simulation have guided the definition of MOZART's syntax, value set, delay model, and algorithms. Performance is improved by reducing unnecessary activity. Two such techniques are levelized: two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Moreover, efficient handling of abnormally large or active fault machines can improve fault-simulator performance by several orders of magnitude. These and related issues are discussed; both analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A performance metric is introduced for fault simulation, based on comparison with the serial algorithm, and is more accurate than those used in the past.>