Restrictions inherent to processors used in the Internet of Things (IoT) devices or the need for area reduction in massively parallel processing systems for artificial intelligence lead to the search of tradeoffs between precision and area in arithmetic operations. In this sense, simple precision enables to save area and to speed up computations when no higher precision is required. On the other hand, iterative methods such as Newton–Raphson’s or Goldschmidt’s allow to reduce or remove the use of memory tables. In these methods, the selection of the initial value or seed is critical to achieve a reasonable precision using the lowest possible number or iterations. In this article, new hardware implementations of seed generators with very low-area requirements are proposed for Square Root and Inverse Square Root, while maintaining good precision, high performance, and low power consumption. A new design methodology, named successive approximation methodology (SUAM), enables to implement seed generators using only a few logic gates. The presented experimental and implementation results support the validity of the developed seed generators.

Motion estimation from image sequences, called optical flow, has been deeply analyzed by the scientific community. Despite the number of different models and algorithms, none of them covers all problems associated with real-world processing. This paper presents a novel customizable architecture of a neuromorphic robust optical flow (multichannel gradient model) based on reconfigurable hardware with the properties of the cortical motion pathway, thus obtaining a useful framework for building future complex bioinspired real-time systems with high computational complexity. The presented architecture is customizable and adaptable, while emulating several neuromorphic properties, such as the use of several information channels of small bit width, which is the nature of the brain. This paper includes the resource usage and performance data, as well as a comparison with other systems. This hardware platform has many application fields in difficult environments due to its bioinspired nature and robustness properties, and it can be used as starting point in more complex systems.

The present work describes a reliable improved gradient optical flow estimation system using FPGAs. This structure is based on space-temporal processing and the use of steerable filters. This model can be enhanced using psychophysical and bioinspired properties according to biological vision in order to mimic the singularity and the performance of mammalians. Experimental results and the resources used to analyze the associate customizability of the system are discussed.

This work describes an analog reconfiguration technique for acquisition and processing of analog sensor signals that involves Field Programmable Analog Arrays (FPAAs) and Field Programmable Gate Arrays (FPGAs). The main objective is to exploit their natural reconfiguration capabilities that allow the increase of the analog-to-digital conversion (ADC) resolution and an adaptive post processing of the digital signal. This work is completed by the demonstration of this technique with an NTC temperature sensor signal, increasing the ADC resolution. The proposed system acquires the analog signal with filtering, amplifications and ADC being performed on the FPAA, while dynamically tuning the analog conditioning on the FPAA; after that, the FPGA processes the digital signal and delivers the final result to the end user, also involving the use of an embedded PicoBlaze.

This paper presents significant improvements to our previous watermarking technique for Intellectual Property Protection (IPP) that enables the protection of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using combinational logic included within the original system. Thus, any attack trying to change or remove the digital signature will damage the design. The technique also includes a procedure for secure signature extraction. The new advances refer to increasing the applicability of this watermarking technique to any design and the provision of an automatic tool for signature hosting purposes. The design examples on FPL devices show the effectiveness of this watermarking technique. Synthesis results show that the application of the proposed watermarking strategy results in negligible degradation of system performance and very low area penalties.

This work describes the application of both Field Programmable Analog Arrays (FPAAs) and Field Programmable Gate Arrays (FPGAs) for signal conditioning and processing in smart sensor applications. The main objective is to exploit their natural reconfiguration capabilities, which will expand the application field to more complex measurement and control systems. On the other hand, the introduction of IEEE 1451-compliant sensors allows for the development of multi-sensor and multi-purpose platforms, that may benefit from programmable technologies. Thus, this paper includes initial developments for IEEE 1451 smart sensor interfacing and its application to instrumentation.

In this paper, a procedure for intellectual property protection (IPP) of digital circuits called IPP@HDL is presented. Its aim is to protect the author rights in the development and distribution of reusable modules by means of an electronic signature. The technique relies on hosting the bits of the digital signature within memory structures or combinational logic that are part of the system, at the high level description of the design. Thus, the area of the system is not increased and the signature is difficult to change or to remove without damaging the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system and without interfering its normal operation. The benefits of the presented procedure are illustrated with programmable logic and cell-based application-specific integrated circuit examples with several signature lengths. These design examples show no performance degradation and a negligible area increase, while probabilistic analyses show that the proposed IPP scheme offers high resistance against attacks.

This paper presents a technique for intellectual property protection (IPP) of systems to be implemented over programmable devices. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The technique relies on a procedure that spreads a digital signature in cells of look-up tables of designs at HDL design level, not increasing the area of the system. The technique includes a procedure for signature extraction requiring minimal modifications to the system. So it is possible to detect the ownership rights without interfering the normal operation of the system. The IPP technique has been implemented on FPL devices, not disrupting the functionality neither significantly degrading the performance.

The discrete wavelet transform is routinely used in numerous applications and its efficient implementation in VLSI technology is a subject of continuous research. This paper shows the implementation of reduced complexity and high performance polyphase wavelet filter banks using Galois field arithmetic. The proposed designs are compared to traditional systems using 2's complement (2C) arithmetic with the proposed architectures being about 65% faster than 2C designs and requiring less logic in most study cases.

The need for both speed and increased precision in modern digital signal processing (DSP) applications represents a serious implementation obstacle. The paper explores the arithmetic benefits provided by the residue number system (RNS) for the design of such systems. Specifically, the fusion of the RNS with the popular distributed arithmetic (DA) is considered for the implementation of a discrete wavelet transform (DWT) filter bank. An exhaustive comparison of the advantages of RNS-DA over the traditional two's complement design, 2C-DA, is carried out for field-programmable logic (FPL), and cell-based ASIC technologies. The results show that the reported RNS-DA methodology, compared to a traditional 2C-DA design, enjoys a significant performance advantage that increases with precision.

A new methodology to compute the N-point DCT (Discrete Cosine Transform) in the QRNS (Quadratic Residue Number System) is presented, with a significant improvement in complexity and speed compared to the corresponding binary version. This reduction in the total number of arithmetic adders and multipliers is up to 21% and 26% for an 8-point and a 16-point DCT, respectively. In addition, large and slow binary adders and multipliers with a long carry propagation delay are replaced by high-speed small word-length modular adders and LUT (Look-Up Table) multipliers. When a Field Programmable Logic (FPL) implementation using Altera FLEX10KE devices of the proposed architecture for the 8-point DCT is considered, throughput is three times better than that obtained with the corresponding fixed point 2's complement binary implementation.

Previous scaling schemes have used iterative algorithms, which lead to computation time and memory requirements that increase with the number of moduli. This paper presents a two look-up cycle scaling scheme which allows a diminution of the required memory when nonlarge sets of moduli are considered. This scheme can be combined with previous algorithms for larger sets of moduli.

Field-programmable logic (FPL) is on the verge of revolutionizing digital signal processing (DSP) in the manner that programmable DSP microprocessors did nearly two decades ago. While FPL densities and performance have steadily improved to the point where some DSP solutions can be integrated into a single FPL chip, they still have limited use in high-precision high-bandwidth applications. It is shown that in such cases, the residue number system (RNS) can be an enabling technology. The design of a high-decimation rate digital filter is presented which demonstrates the RNS-FPL synergy.