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R. Galivanche

dblp:00/2275 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 77% Parallel and multicore computing · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis		 0.011987
A Parallel PLA Minimization Program · DAC 1987
Electronic design automation › logic synthesis › programmable logic array
PLA optimization		 0.011987
A Parallel PLA Minimization Program · DAC 1987
Parallel and multicore computing
parallel programming models		 0.011987
A Parallel PLA Minimization Program · DAC 1987
Parallel and multicore computing › parallel programming models
shared-memory parallelization		 0.011987
A Parallel PLA Minimization Program · DAC 1987

Methods — techniques the papers use, named apart from their topics

ESPRESSO-MV · 0.0
YearPublicationVenuePosition
1987 A Parallel PLA Minimization Program
abstract
In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The parallel algorithm was implemented on a shared memory multicomputer system. In the course of development of the parallel algorithm, some changes were made to ESPRESSO-MV which resulted in lower computing time. Experimental results using 105 PLAs are included.
R. Galivanche, Sudhakar M. Reddy
 DAC1