Resistive nonvolatile memories (NVMs) promise significant performance improvement over existing NVM candidates. However, fabrication nonidealities and parasitics on the access path cause cell location-dependent variations in the total resistance received at the read circuitry. Write characteristics delivered to each cell, as well as the optimal write conditions for each cell, are also location-dependent. In this article, we propose a 2-D calibration scheme to address these variations. The proposed scheme joins row and column calibrations to create a correction grid at each crosspoint on the array and effectively cancels many spatial patterns. The enabling circuit and algorithmic modifications are described. We assess the 2-D calibration scheme in a 28-nm$256\times 256$memory array, and show reduction in variability across multiple gradient patterns compared to conventional calibration methods. For the same calibration granularity, 2-D calibration achieves between 41% and 99% improvement depending on the amount of calibration bits. For the same amount of total calibration bits, the 2-D calibration scheme reduces the variability between 39% and 99%.

The extreme complexity of the brain has attracted the attention of neuroscientists and other researchers for a long time. More recently, the neuromorphic hardware has matured to provide a new powerful tool to study neuronal dynamics. Here, we study neuronal dynamics using different settings on a neuromorphic chip built with flexible parameters of neuron models. Our unique setting in the network of leaky integrate-and-fire (LIF) neurons is to introduce a weak noise environment. We observed three different types of collective neuronal activities, or phases, separated by sharp boundaries, or phase transitions. From this, we construct a rudimentary phase diagram of neuronal dynamics and demonstrate that a noise-induced chaotic phase (N-phase), which is dominated by neuronal avalanche activity (intermittent aperiodic neuron firing), emerges in the presence of noise and its width grows with the noise intensity. The dynamics can be manipulated in this N-phase. Our results and comparison with clinical data is consistent with the literature and our previous work showing that healthy brain must reside in the N-phase. We argue that the brain phase diagram with further refinement may be used for the diagnosis and treatment of mental disease and also suggest that the dynamics may be manipulated to serve as a means of new information processing (e.g., for optimization). Neuromorphic chips, similar to the one we used but with a variety of neuron models, may be used to further enhance the understanding of human brain function and accelerate the development of neuroscience research.

In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected on die. These components are then used to realize FIR filter and AdaBoost (machine-learning algorithm). 3X–37X energy advantage is shown for the proposed SC compared with CMOS binary arithmetic ASIC and SC designs.

A word line pulse (WLP) circuit scheme is proposed toward the implementation of magnetoelectric random access memory (MeRAM). The circuit improves the write error rate (WER) and cell area efficiency by generating a better write pulse compared to conventional bitline pulse (BLP) techniques in terms of the pulse slew rate and amplitude. For the voltage-controlled magnetic anisotropy-induced precessional switching of the magnetic tunnel junction (MTJ), the write pulse shape has a large impact on the switching probability. Typically, a square shape pulse results in higher switching probability compared to that of a triangular shape pulse with long rise and falling edges, since the square shape pulse causes a more stable precessional trajectory of the free layer magnetization by providing a relatively constant in-plane-dominant effective field. Compared to the BLP scheme, the WLP can generate a better square shape pulse by eliminating discharge paths under the pulse condition, using the gain of the access transistor, and effectively diminishing the capacitive loading which needs to be driven. A macrospin compact model of voltage-controlled MTJ shows that the WLP can improve WER by${10}^{7}$times and allow MeRAM to have four-time improvement in area efficiency of driver circuits compared to the BLP.

Spin-transfer torque random access memory (STT-RAM) and magnetoelectric random access memory (MeRAM) are promising non-volatile memory technologies. But STT-RAM and Me RAM both suffer from high write error rate due to thermal fluctuation of magnetization. Temperature and wafer-level process variation significantly exacerbate these problems. In this paper, we propose a design that adaptively selects optimized write pulse for STT-RAM and MeRAM to overcome ambient process and temperature variation. To enable the adaptive write, we design specific MTJ-based variation monitor, which precisely senses process and temperature variation. The monitor is over 10X faster, 5X more energy-efficient, and 20X smaller compared with conventional thermal monitors of similar accuracy. With adaptive write, the write latency of STT-RAM and MeRAM cache are reduced by up to 17% and 59% respectively, and application run time is improved by up to 41%.

A non-volatile spintronic programmable logic (SPL), based on a 3-teriminal magnetic tunnel junction (MTJ), is presented and simulated using a compact device model. The SPL structure is compatible with CMOS technology and can be fabricated in the back end of line (BEOL). The proposed SPL exploits the gate-voltage-modulated spin Hall effect (V-SHE) switching, which combines the voltage controlled magnetic anisotropy (VCMA) effect and SHE, as a parallel configuration method. The VCMA modulates the coercivity of the MTJ, reducing the critical current for the SHE to change the state of MTJs. This allows the SPL to achieve 100x faster configuration speed due to the parallel configuration, and 32% area reduction because of minimized transistors in the write circuit, compared to conventional spin transfer torque memory (STT-RAM) based programmable logic.

Spintronics is regarded as a promising solution for resolving the major challenging issues related to the scaling of Si-based complementary metal–oxide–semiconductor (CMOS) technology as it offers the advantages of combing the spin and charge degrees of freedom. After decades of progress, the quintessence to achieve practical low-dissipation applications lies in the ability to manipulate magnetic states by electric field via several different physical mechanisms. Among them, the emergence of the spin-orbit coupling engineering has been shown to dramatically reduce energy dissipation and improve the performance as well as to multiply spintronic device possibilities and functionalities for a new generation of ultralow-power nonvolatile spintronic systems. This article provides a review of the current development including fundamental physics and experimental implementations of electric-field-controlled ferromagnetism in dilute magnetic semiconductors, voltage control of magnetic anisotropy, spin-orbit-torque-assisted magnetization switching, and antiferromagnetic (AFM) material-based spin-orbitronic systems. We provide an assessment in terms of scaling of energy, speed, and size. Finally, we offer an outlook of electric-field-controlled spintronic applications, particularly in view of their integration with CMOS to form hybrid spintronic circuits.

Variability effects in graphene can result from the surrounding environment and the graphene material itself, which form a critical issue in examining the feasibility of graphene devices for large-scale production. From the reliability and yield perspective, these variabilities cause fluctuations in the device performance, which should be minimized via device engineering. From the metrology perspective, however, the variability effects can function as novel probing mechanisms, in which the “signal fluctuations” can be useful for potential sensing applications. This paper presents an overview of the variability effects in graphene, with emphasis on their challenges and opportunities for device engineering and applications. The discussion can extend to other thin-film, nanowire, and nanotube devices with similar variability issues, forming general interest in evaluating the promise of emerging technologies.

Based on projections of the International Roadmap for Semiconductors (ITRS), the continued scaling of complementary metal–oxide semiconductor (CMOS) devices will face severe technical challenges. Among the most critical are power dissipation and device-level variabilities that will make circuit design very difficult. Potential device-level solutions that take advantage of new functional materials, self-assembly processes, low dissipation nanoscale devices, and architectures that aim in sustaining Moore's law beyond the ITRS are discussed in this paper. Two potential paths forward are clear at this point. One path is to continue increasing chip-scale functional throughput by looking at new functional materials at atomic and molecular levels for assembly into new low-power devices with different logic state variables that can better tolerate variabilities. Another distinct approach is to increase chip-scale functionality by exploiting the heterogeneous integration of materials, such as compound semiconductors on silicon as enabled by the unique features in nanoscale epitaxy and self-assembly on a common substrate. This paper will discuss some possible methods forward in maintaining scaled CMOS and going beyond the roadmap.

In this article, we present a nanoscale reconfigurable mesh which is interconnected by ferromagnetic spin-wave buses. In this architecture, unlike the traditional spin-based nano structures which transmit charge, waves are transmitted. As a result, the power consumption of the proposed modules can be low. This reconfigurable mesh, while requiring the same number of switches and buses as the standard reconfigurable mesh, is capable of simultaneously transmitting N waves on each of the spin-wave buses. Because of this highly parallel feature, very fast and fault-tolerant algorithms can be designed. To illustrate the superior performance of the proposed spin-wave reconfigurable mesh, we present three fast labeling algorithms.

In recent years, quantum dots have been successfully grown by self-assembling processes. For optoelectronic device applications, the quantum-dot structures have advantages such as reduced phonon scattering, longer carrier lifetime, and lower detector noise due to low-dimensional confinement effect. Comparing to traditional optoelectronic III-V and other materials, self-assembled Ge quantum dots grown on Si substrates have a potential to be monolithically integrated with advanced Si-based technology. In this paper, we describe the growth of self-assembled, guided Ge quantum dots, and Ge quantum-dot superlattices on Si. For dot growth, issues such as growth conditions and their effects on the dot morphology are reviewed. Then vertical correlation and dot morphology evolution are addressed in relation to the critical thickness of Ge quantum-dot superlattices. In addition, we also discuss the quantum-dot p-i-p photodetectors (QDIPs) and n-i-n photodetectors for mid-infrared applications, and the quantum-dot p-i-n photodetectors for 1.3–1.55$\mu{\hbox {m}}$for communications applications. The wavelength of SiGe p-i-p QDIP can be tuned by the size as grown by various patterning methods. Photoresponse is demonstrated for an n-i-n structure in both the mid-infrared and far-infrared wavelength ranges. The p-i-n diodes exhibit low dark current and high quantum efficiency. The characteristics of fabricated light-emitting diode (LED) devices are also discussed, and room-temperature electroluminescence is observed for Ge quantum-dot LED. The results indicate that Ge dot materials are potentially applicable for mid-infrared (8–12$\mu{\hbox {m}}$) detectors as well as fiber-optic (1.3–1.55$\mu{\hbox {m}}$) communications.