A parallel architecture is proposed for a high speed query server to process postal addresses with several fields. For a given component in a field, the offset addresses of records which contain the component in a postal address database are coded into a Compressed Bit Vector (CBV). Finding the appropriate CBVs and performing intersections to get matching offset addresses are key bottleneck for the performance in the query server. They are accomplished by a specialized hardware embedded in a general purpose computer for a cost effective solution. This hardware directly operates on the CBVs using parallel schemes. The architecture and algorithms for expanding a CBV, for synchronizing the parallel processing of the processing units, and for balancing the load in the pipelined stages are presented with simulation results.