Progress in human behavior modeling involves understanding both implicit, early-stage perceptual behavior, such as human attention, and explicit, later-stage behavior, such as subjective preferences or likes. Yet most prior research has focused on modeling implicit and explicit human behavior in isolation; and often limited to a specific type of visual content. We propose UniAR -- a unified model of human attention and preference behavior across diverse visual content. UniAR leverages a multimodal transformer to predict subjective feedback, such as satisfaction or aesthetic quality, along with the underlying human attention or interaction heatmaps and viewing order. We train UniAR on diverse public datasets spanning natural images, webpages, and graphic designs, and achieve SOTA performance on multiple benchmarks across various image domains and behavior modeling tasks. Potential applications include providing instant feedback on the effectiveness of UIs/visual content, and enabling designers and content-creation models to optimize their creation for human-centric improvements.

Power is the number one implementation challenge for many consumer SoCs, especially in the telecommunications and mobile space. A large portion of that, 30% or more, can be directly attributed to the clock tree. 10-20% additional power can additionally be attributed to increased logic area on account of skew in the clock tree. Increasingly, we find designers trying to reduce power both by manual specifications of multiple voltage and power domains, block and core level clock gating as well as more automated techniques like leaf-level combinational and sequential clock gating. However, this tends to increase the problem complexity for the clock tree synthesis tool. Furthermore, these numbers are only likely to get worse with larger designs and more complex clocking scenarios. Already it is not uncommon to see over 200 clocks defined for a modern SoC; several of them asynchronous to each other in the timing sense; but which nevertheless overlap physically. This creates a nightmare problem instance for traditional clock tree synthesis tools attempting to balance path delays to all sinks. Further, due to DFT and other design considerations, the clock tree network is increasingly resembling more a regular logic network of gates rather than a simple buffer tree with the occasional clock gates.

Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, embedded memories and custom RTL blocks. At current and future technology nodes, their power and performance are impacted, more than ever, by the placement of their modules. However, our experiments show that traditional techniques for placement and floorplanning, and existing academic tools cannot reliably solve the placement task. To study this problem, we identify particularly difficult industrial instances and reproduce the failures of existing tools by modifying public-domain netlists. Furthermore, we propose algorithms that facilitate floorplacement of these difficult instances. Empirically, our techniques consistently produced legal placements, and on instances where comparison is possible, reduced wirelength by 3.5% over Capo 9.4 and 14.5 % over PATOMA 1.0 — the pre-existing tools that most frequently produced legal placements in our experiments.