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Vikram Dhar

dblp:00/3407 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 56% Energy-efficient computing · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
branch prediction
0.112008
PaCo: Probability-based path confidence prediction · HPCA 2008
Energy-efficient computing › power management › fine-grain power management
pipeline gating
0.112008
PaCo: Probability-based path confidence prediction · HPCA 2008
Processor architecture and microarchitecture › multithreading
simultaneous multithreading
0.012008
PaCo: Probability-based path confidence prediction · HPCA 2008

Methods — techniques the papers use, named apart from their topics

probability estimation · 0.1prediction · 0.1
YearPublicationVenuePosition
2008 PaCo: Probability-based path confidence prediction
abstract
A path confidence estimate indicates the likelihood that the processor is currently fetching correct path instructions. Accurate path confidence prediction is critical for applications like pipeline gating and confidence-based SMT fetch prioritization. Previous work in this domain uses a threshold-and-count predictor, where the number of unresolved, low-confidence branches serves as an estimate of path confidence. This approach is inaccurate since it implicitly assumes that all low-confidence branches have the same mispredict rate, and that high-confidence branches never mispredict. We propose an alternative path confidence predictor designed from first principles, called PaCo, that directly estimates the probability that the processor is on the goodpath, and considers contributions from all branches, both high and low confidence. Even though it uses only modest hardware, PaCo can estimate the processor’s goodpath likelihood with very high accuracy, with an RMS error of 3.8%. We show that PaCo significantly outperforms threshold-and-count predictors in pipeline gating and SMT fetch prioritization. In pipeline gating, while the best conventional predictor can reduce badpath instructions executed by 7% with a small loss in performance, PaCo can reduce bad-path instructions by 32% without any performance loss. In SMT fetch prioritization, using PaCo instead of conventional path confidence predictors improves performance by up to 23%, and 5.5% on average.
Kshitiz Malik, Mayank Agarwal, Vikram Dhar, Matthew I. Frank
HPCA3