In the past decade and a half, physical unclonable functions (PUFs) have been introduced as a promising cryptographic primitive for hardware security applications. Since then, the race between proposing new complex PUF architectures and new attack schemes to break their security has been ongoing. Although modeling attacks using conventional machine learning techniques were successful against many PUFs, there are still some delay-based PUF architectures which remain unbroken against such attacks, such as the double arbiter PUFs. These stronger complex PUFs have the potential to be a promising candidate for key generation and authentication applications. This paper presents an in-depth analysis of modeling attack using deep learning (DL) techniques against double arbiter PUFs (DA-PUFs). Unlike more conventional machine learning techniques such as logistic regression and support vector machines, DL results show enhanced prediction accuracy of the attacked PUFs, thus pushing up the boundaries of modeling attacks to break more complex architectures. The attack on 3-1 DAPUFs has improved accuracy of over 86% (compared to previous research achieving a maximum of 76%) and the 4-1 DAPUFs accuracy ranges between 71%-81.5% (compared to previous research of maximum 63%). This research is crucial for analyzing security of existing and future PUF architectures, confirming that as DL computations become more widely accessible, designers will need to hide the PUFs CRP relationship from attackers.

Recently electromagnetic fault injection (EMFI) techniques have been found to have significant implications on the security of embedded devices. Unfortunately there is still a lack of understanding of EM fault models and countermeasures for embedded processors. For the first time, this paper proposes an extended fault model based on the concept of critical charge and a new EMFI backside methodology based on over-clocking. Results show that exact timing of EM pulses can provide reliable repeatable instruction replacement faults for specific programs. An attack on AES is demonstrated showing that the EM fault injection requires on average less than 222 EM pulses and 5.3 plaintexts to retrieve the full AES key. This research is critical for ensuring embedded processors and their instruction set architectures are secure and resistant to fault injection attacks.

A fundamental property of Physical Unclonable Functions (PUFs) is uniqueness, which results from the intrinsic characteristics of each PUF instance. However, PUF architectures employ elements whose physical characteristics and behavior may be very similar among different instances, thus leaking unwanted information. We explore the consequences of this effect by mounting Template Attacks over XOR Arbiter PUFs. In the attack, Challenge-Respose Pairs (CRPs) are profiled in one FPGA instance of the PUF to predict responses of a different FPGA instance, obtaining up to 80% of accuracy. We show that replicating the same attack strategy with a well-known Machine Learning (ML) algorithm would not be as effective, since different PUFs instances will not share similar CRP sets. Our template attack only needs few CRPs for profiling (at most 170), but it can be applied to different instances without additional training, which Machile Learning cannot do with unbiased PUF instances.

Although HMAC-SHA has been standardized for over a decade, few published attacks on the single-cycle round implementation exist. In this research, new attack techniques are provided, for the first time, (1) to help to discriminate between values of secret intermediate variables within HMAC and (2) to reduce the large word size complexity. Preaveraging and carry propagate techniques are proposed using chosen plaintexts and shown to significantly reduce the complexity and runtimes for side-channel analysis of an Altera FPGA platform. This research is important for advancing side channel analysis of complex embedded ASICs and ensuring secure implementations in future embedded ubiquitous devices.

Future wireless embedded devices will be increasingly powerful, supporting many more applications including one of the most crucial, security. Although many embedded devices offer resistance to bus probing attacks due to their compact size and high levels of integration, susceptibility to attacks on their electromagnetic side channel must be analyzed. This side channel is often quite complex to analyze due to the complexities of the embedded device including operating system, interrupts, and so forth. This article presents a new methodology for analyzing a complex system's vulnerability to the EM side channel. The methodology proposes a sliding window phase-only correlation method for aligning electromagnetic emanations from a complex smartphone running native code utilizing an on-chip cache. Unlike previous research, experimental results demonstrate that data written to on-chip cache within an advanced 312MHz 0.13um processor executing AES can be attacked utilizing this new methodology. Furthermore, for the first time, it has been shown that the point of side-channel attack is not a spike of increased EM but an area of low EM amplitude, unlike what is noted in previous findings. This research is important for advancing side-channel analysis understanding in complex embedded processors and ensuring secure implementations in future embedded ubiquitous devices.

Dynamic and Differential Logics (DDLs) used for providing resistance against power analysis consume significant area. In order to tackle the area cost this paper examines using a Static and Single-ended Logic (SSL) for designing gates and registers which are resistant against power analysis. Current-Balanced Logic (CBL) is chosen and an empirical analysis is conducted for evaluating the effectiveness of CBL in a test chip fabricated in 0.18µm CMOS process. The increased resistance obtained by CBL requires significantly less area than the previously reported logic level countermeasures. No complex layout methodology as the one used for DDL is needed for implementation of CBL. The results presented in this paper are important for providing resistance against power analysis for area-constrained applications with no battery operated supply.

Remote update of hardware platforms or embedded systems is a convenient service enabled by Field Programmable Gate Array (FPGA)-based systems. This service is often essential in applications like space-based FPGA systems or set-top boxes. However, having the source of the update be remote from the FPGA system opens the door to a set of attacks that may challenge the confidentiality and integrity of the FPGA configuration, the bitstream. Existing schemes propose to encrypt and authenticate the bitstream to thwart these attacks. However, we show that they do not prevent the replay of old bitstream versions, and thus give adversaries an opportunity for downgrading the system. In this article, we propose a new architecture called sarfum that, in addition to ensuring bitstream confidentiality and integrity, precludes the replay of old bitstreams. sarfum also includes a protocol for the system designer to remotely monitor the running configuration of the FPGA. Following our presentation and analysis of the security protocols, we propose an example of implementation with the CCM (Counter with CBC-MAC) authenticated encryption standard. We also evaluate the impact of our architecture on the configuration time for different FPGA devices.

The susceptibility of wireless portable devices to electromagnetic (EM) attacks is largely unknown. If analysis of electromagnetic (EM) waves emanating from the wireless device during a cryptographic computation do leak sufficient information, it may be possible for an attacker to reconstruct the secret key. Possession of the secret cryptographic key would render all future wireless communications insecure and cause further potential problems, such as identity theft. Despite the complexities of a PDA wireless device, such as operating system events, interrupts, cache misses, and other interfering events, this article demonstrates that, for the first time, repeatable EM differential attacks are possible. The proposed differential analysis methodology involves precharacterization of the PDA device (thresholding and pattern recognition), and a new frequency-based differential analysis. Unlike previous research, the new methodology does not require perfect alignment of EM frames and is repeatable in the presence of a complex embedded system (including cache misses, operating system events, etc), thus supporting attacks on real embedded systems. This research is important for future wireless embedded systems, which will increasingly demand higher levels of security.

Future wireless embedded devices will be increasingly powerful, supporting many more applications, including one of the most crucial---security. Although many embedded devices offer more resistance to bus---probing attacks because of their compact size, susceptibility to power or electromagnetic analysis attacks must be analyzed. This paper presents a new split-mask countermeasure to thwart low-order differential power analysis (DPA) and differential EM analysis (DEMA). For the first time, real-power and EM measurements are used to analyze the difficulty of launching new third-order DPA and DEMA attacks on a popular low-energy 32-bit embedded ARM processor. Results show that the new split-mask countermeasure provides increased security without large overheads of energy dissipation, compared to previous research. With the emergence of security applications in PDAs, cell phones, and other embedded devices, low-energy countermeasures for resistance to low-order DPA/DEMA is crucial for supporting future enabled wireless internet.

Future wireless embedded devices will be increasingly powerful, supporting many more applications, including one of the most crucial, which is security. Although many embedded devices offer more resistance to bus probing attacks due to their compact size, susceptibility to power or electromagnetic analysis attacks must be analyzed. This paper presents a table masking countermeasure to resist differential power analysis (DPA) and differential electromagnetic analysis (DEMA). Real power and EM measurements are used to verify the countermeasure using second- and third-order DPA and DEMA attacks on a popular low-energy embedded ARM processor. Results show that the new table masking countermeasure provides increased security without large overheads of energy dissipation compared with previous countermeasures. With the emergence of security applications personal digital assistants, cellphones, and other embedded devices, low-energy countermeasures for resistance to DPA/DEMA are crucial for supporting future wireless embedded systems

Measuring and modeling instantaneous current consumption or current dynamics of a processor is important in embedded system designs, wireless communications, low-energy mobile computing, security of communications, and reliability. In this paper, we introduce a new instruction-level based macromodeling approach for instantaneous current consumption in a complex processor core along with new instantaneous current measurement techniques at the instruction and program level. Current consumption and voltage supply waveforms of a processor core were acquired by a sampling oscilloscope through an external interrupt-based setup. Accurate measurements of current, power and energy consumption at the instruction, block, or program level were obtained from analyzing the stored current and voltage waveforms. The current simulation methodology uses elementary functions called atomic functions to approximate the instantaneous current consumption at the instruction level. Based on these atomic functions, a simulated instantaneous current waveform at the program level was built. First, a base waveform of the current simulation was generated by the use of four basic current superposition principles. Secondly, a final waveform of the simulated current was generated from the base waveform by applying a factorial adjustment as a function of the instruction parallelism and sequencing. Step-by-step modeling procedures with numerical examples are presented. The model captured 98% of the variation of the instantaneous current for six complex applications, with an average RMS error of less than 2.2% of the average measured mean. Energy estimates obtained by the use of the simulated current waveforms were within 1.4% of the measured values. This research is important, since for the first time highly accurate instruction-based models of instantaneous current and power for complex processor cores have been developed.

Embedded wireless devices require secure high-performance cryptography in addition to low-cost and low-energy dissipation. This paper presents for the first time a design methodology for security on a VLIW complex DSP-embedded processor core. Elliptic curve cryptography is used to demonstrate the design for security methodology. Results are verified with real dynamic power measurements and show that compared to previous research a 79% improvement in performance is achieved. Modification of power traces are performed to resist simple power analysis attack with up to 39% overhead in performance, up to 49% overheads in energy dissipation, and up to 11% overhead in code size. Simple power analysis on the VLIW DSP core is shown to be more correlated to routine ordering than individual instructions. For the first time, differential power analysis results on a VLIW using real power measurements are presented. Results show that the processor instruction level parallelism and large bus size contribute in making differential power analysis attacks extremely difficult. This research is important for industry since efficient yet secure cryptography is crucial for wireless communication devices.

This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors, 16-bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses, including constant data-memory layout, while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size and utilize higher-memory bandwidths without increasing cost.

This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors, such as Star*core, sixteen bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth (and up to 30% reduction in energy dissipation) are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can increase memory bandwidths and minimize code size without increasing cost.

This paper presents an empirical approach to inferring low power code generation techniques for VLIW processors. Architectural usage variables are used to generate equations for power prediction which are in turn used to infer new code generation techniques for low power. Unlike previous techniques, the methodology empirically derives a power prediction equation and then based upon the coefficients of the architectural-usage variables identifies new VLIW code generation techniques for low power. The approach is illustrated using functional unit usage within a VLIW architecture and identifies a new operation rebinding technique for low power which improved power dissipation up to 18%. The approach is general and results are verified with real power measurements. This result is important for developing a general methodology for power minimization of embedded DSP software since low power is critical to complex DSP applications in many cost sensitive markets.

This paper presents a new approach to solving the DSP address code generation problem. A minimum cost circulation approach is used to efficiently generate high-performance addressing code in polynomial time. Results show that addressing code size improvements of up to 6/spl times/ are obtained, accounting for up to 1.6/spl times/ improvement in code size and performance of compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size, energy dissipation, and performance, without increasing cost.

This paper presents a comparison of statistically-derived power prediction models at the algorithmic, instruction, and architectural levels for embedded high performance DSP processors. The approach is general enough to be applied to any embedded DSP processor. Results from 168 power measurements of DSP code show that power can be predicted at instruction and architecture levels with less than 2% error. This result is important for developing a general methodology for power characterization of embedded DSP software since low power is critical to complex DSP applications in many cost sensitive markets.

This paper presents for the first time low energy simultaneousmemory and register allocation. A minimum cost network flowapproach is used to efficiently solve for minimum energy dissipationsolutions in polynomial time. Results show that estimatedenergy improvements of 1.4 to 2.5 times over previous researchare obtained. This research is important for industry since energydissipation is minimized without requiring an increase in cost.

This paper presents a new approach to solving the DSP address assignment problem. A minimum cost circulation approach is used to efficiently generate high performance addressing code in polynomial time. Addressing code size improvements of up to 7 times are obtained, accounting for up to 1.6 times improvement in code size and performance of compiler-generated DSP code. Results also show that memory layout has a small effect on code size and performance when optimal addressing is used. This research is important for industry since this value-added technique can improve code size, power dissipation and performance, without increasing cost.

An optimization approach to the high level synthesis of VLSI multichip architectures is presented in this paper. This research is important for industry since it is well known that these early high level decisions have the greatest impact on the final VLSI implementation. Optimal application-specific architectures are synthesized here to minimize latency given constraints on chip area, I/O pin count and interchip communication delays. A mathematical integer programming (IP) model for simultaneously partitioning, scheduling, and allocating hardware (functional units, I/O pins, and interchip busses) is formulated. By exploiting the problem structure, using polyhedral theory, the size of the search space is decreased and a new variable selection strategy is introduced based on the branch and bound algorithm. Multichip optimal architectures for several examples are synthesized in practical cpu times. Execution times are comparable to previous heuristic approaches, however there are significant improvements in optimal schedules and allocations of multichips. This research breaks new ground by 1) simultaneously partitioning, scheduling, and allocating in practical cpu times, 2) guaranteeing globally optimal architectures for multichip systems for a specific objective function, and 3) supporting interchip communication delay, interchip bus allocation, and other complex interface constraints.>

A relaxed linear programming model which simultaneously schedules and allocates functional units and registers is presented for synthesizing cost-constrained globally optimal architectures. This approach is important for industrial applications, because it provides exploration of optimal synthesized architectures and early architectural decisions have the greatest impact on the final design. An integer programming formulation of the architectural synthesis problem is transformed into the mode packing problem. Polyhedral theory is used to formulate constraints that decrease the size of the search space, thus improving solution efficiency. Execution times are an order of magnitude faster than for previous heuristic techniques. The present approach breaks new ground by (1) simultaneously scheduling and allocating in practical execution times, (2) guaranteeing globally optimal solutions for a specific objective function, and (3) providing a polynomial run-time algorithm for solving some instances of this NP-complete problem.>

This paper presents for the first time an optimization approach to synthesizing DSP-specific architectures which maximize throughput. A new integer programming (IP) model is presented that supports simultaneous scheduling, allocation, and retiming or loop winding. The IP model is used to map a DSP application to a high speed application-specific architecture which maximizes throughput given constraints on area and latency. Results show this approach optimally synthesizes architectures that have up to 12% higher throughputs than previously published architectures. This research provides industry with a DA tool for mapping DSP applications to high performance architectures optimized for throughput.>

A global optimization approach to high level synthesis of VLSI multichip architectures is presented. Optimal application-specific architectures are synthesized to minimize latency given constraints on chip area, I/O pin count and interchip communication delays. A mathematical integer programming (IP) model for simultaneously partitioning, scheduling, and allocating hardware (functional units, I/O pins, and interchip buses) is formulated. By exploiting the problem structure (using polyhedral theory), the size of the search space is decreased and a new variable selection strategy is introduced based on the branch and bound algorithm. Multichip optimal architectures for several examples are synthesized in practical CPU times. Execution times are comparable to those for previous heuristic approaches. There are, however, significant improvements in optimal schedules and allocations of multichips.>

An integer programming (IP) model, which simultaneously schedules and allocates functional units, registers, and busses, is presented for synthesizing cost-constrained globally optimal architectures. This research is important for industry by providing optimal schedules which minimize interconnect costs and interface to analog and asynchronous processes, since these are seen as key to synthesizing high performance architectures. A partially structured tight IP formulation of the architectural synthesis problem provides globally optimal schedules for peicewise linear cost functions, using branch and bound, in execution times faster than previous research. This research breaks new ground by 1. simultaneously scheduling and allocating hardware resources including interconnect, 2. support for asynchronous and analog interfaces, and 3. guaranteeing globally optimal solutions in practical execution times.

A relaxed LP model, which simultaneously schedules and allocates functional units and registers, is presented for synthesizing cost-constrained globally optimal architectures. A mathematical integer programming formulation of the architectural synthesis problem was transformed into the node packing problem. Some integral facets of this polytope were extracted and generalized to produce integral solutions using the simplex algorithm without the need to branch and bound. Execution times are faster by an order of magnitude than previous research which makes use of heuristic techniques. This research breaks ground by simultaneously scheduling and allocating with practical execution times; guaranteeing globally optimal solutions for a specific objective function; and providing a polynomial runtime algorithm for solving this NP-complete problem.>

An integrated design and test synthesis methodology is presented with area, delay, and test cost constraints. This methodology, called CATREE2, differs from other approaches by simultaneously synthesizing the normal and test mode design behavior. It is particularly suited for top-down system design where a VLSI component's behavior and test method have been fully specified. Preliminary results show that better design solutions are obtained by considering test incorporation during design synthesis than other methods which incorporate test after a structural design solution is formed.>