In this paper, we build a general modelling framework for memristors, suitable for the simulation of event-based systems such as hardware spiking neural networks, and more generally, neuromorphic computing systems composed of three independent components: i) an event-based modelling approach, extending and generalising an existing general model of memristors - the Generalised Metastable Switch Model (GMSM) [1] - eliminating errors associated with discrete time approximation, as well as offering potential improvements in terms of suitability for neuromorphic memristive system simulations; ii) a volatility state variable to allow for the unified understanding of disparate non-linear and volatile phenomena, including state relaxation, structural disruption, Joule heating, and non-linear drift in different memristive devices; and iii) a readout equation that separates the latent state variable evolution from explicit variables of interest such as an instantaneous resistance. We exhibit an illustrative implementation of this framework, fit to a resistive drift dataset for titanium dioxide memristors, based on a proposed linear conductance model for resistive drift in the devices. Finally, we highlight the application of the model to neuromorphic computing, through demonstrating the contribution of the volatility state variable to switching dynamics, resulting in frequency-dependent switching (for stable memristors acting as programmable synaptic weights) and the generation of action potentials (for unstable memristors, acting as spike-generators).

This paper proposes a Vref-compensated memristor-assisted CDAC background calibration scheme for Nyquist SAR ADCs. The proposed CDAC is implemented in a 12-bit 5 MS/s asynchronous SAR ADC featuring a Vcm-based switching scheme and designed using a standard 65 nm CMOS process. Capacitor mismatches are detected by introducing a redundant bit, which evaluates the sign of the mismatch error. This error is then calibrated through a feedback loop using voltage dividers with four integrated memristors. These programmable voltage dividers generate a compensating voltage that is added to or subtracted from the ADC reference voltage (Vref) based on the sign of the mismatch error. Consequently, the adjusted Vrefcompensates the CDAC output level to reduce non-linearity induced by capacitor mismatches. Simulation results validate the feasibility of optimizing non-linearity in moderate/high-resolution SAR ADCs (12-bit in this study) caused by capacitor mismatches, improving the signal-to-noise-and-distortion ratio (SNDR) from 41.85 dB to 65.98 dB with memristor-assisted analog circuits. The proposed SAR ADC occupies 0.0153 mm2area according to the layout floorplan, making it a promising candidate for miniature/large-scale sensor interface application.

Memristors have emerged as promising candidates for multilevel data storage, in-memory processing, and neural networks since their intrinsic programmability of resistance states under applied stimuli has been well revealed in memristor modeling. However, the programming uncertainty arising from the inherently stochastic nature of the device itself has been overlooked in previous modeling approaches. This omission hinders the incorporation of memristor stochasticity into time-domain circuit simulation. To address this issue, we propose a behavior model that incorporates real-time programming stochasticity. Our model stands out for several attributes: 1) programming stochasticity is included and exhibited in its resistance change over time; 2) its stochastic behavior is depicted by the summation of its deterministic behaviors and a noise signal; and 3) both deterministic behaviors and noise amplitudes depending on the pulse amplitude v and the memristor resistance R are determined by sufficient characterization data of our in-house TiO2 devices in a data-driven method. Consequently, our model is validated as highly matched to the characterized memristor device in terms of time-domain resistance evolution. Additionally, the modeling process can be adapted to different memristors with significant device variations. Furthermore, the model is transformed into the standard Verilog-A style for in-circuit simulation. To demonstrate its compatibility with system-level circuit simulation, a mixed-signal CMOS circuit is designed. This circuit explores the feasibility of storing multibit data within a single memristor, while considering its stochasticity.

In this paper we present a novel memristive circuit that is capable of generating tunable stochastic distributions. The proposed circuit leverages the inherent read noise of the memristor and utilises feedback to shape its spectrum into achieving control over the output distributions mean and standard deviation. We analyse the relationship between various loop parameters and the output noise characteristics of the circuit. We experimentally build the circuit and investigate the output distributions for a range of circuit parameters. Lastly, we develop the theory, propose a system and demonstrate an example, where such circuits generate tunable distributions in hardware for Bayesian Inference and Monte-Carlo sampling.

In this paper, we study the stochastic state trajectory and conductance distributions of memristors under periodic pulse excitation. Our results, backed by experimental evidence, reveal that practical memristors exhibit a$1/f^{2}$Brownian noise power spectrum. Based on this, we develop a Memristive Distribution Generator (MDG) circuit that produces tunable analog distributions by exploiting the physical stochasticity of memristors. By encoding the prior distributions of Bayesian problems in the physical output samples of these circuits, we demonstrate that Monte-Carlo sampling can be devised without knowledge of the analytical output distribution of the memristor. Using examples of 1-D Bayesian linear regression and a dynamic 2-D nonlinear localisation problem, we show how MDG circuits can act as a tunable source of randomness, efficiently representing distributions of interest. Our results, obtained using Pt/TiO2/Pt memristors, validate the use of memristor-based MDGs for implementing probabilistic algorithms.

The design cycle of analog and mixed signal (AMS) components requires the designer to iteratively perform analog simulations, layout, fabrication, and hardware testing. Unlike digital designs, system verification is a difficult task in analog designs, primarily due to a lack of emulation. Thus, a method to emulate AMS components on digital hardware would be highly beneficial. In this work, a high-quality factor crystal oscillator circuit is implemented on a Xilinx Vertex 7 field-programmable gate array (FPGA) using the wave digital filter (WDF) based model with a nonlinear lookup table for modeling transistor characteristics. The number of required hardware resources was minimized while ensuring that the accuracy of the emulation shows an almost perfect match with the SPICE simulations. The WDF model was designed with a tree structure so that it only requires 32 clock cycles to compute a complete sample. The resulting emulation computes a sample at 18.75 MHz while running on an FPGA with a 600 MHz clock.

The natural similarity between the emerging memristive technology and synapses makes memristor a promising device in the spiking input based neuromorphic systems. However, while asynchronous signal processing relies on memristor's response under the pulses stimulus, hardly any memristor models take the impact of sequences features on device behaviour into account. This paper proposes an optimized data-driven compact memristor model where the boundary of its internal state variable-resistive state (RS) is modelled with pulse amplitude and pulse width based on characterisation data. The model has been developed in Verilog-A and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. Based on the simulation, we further introduce a new concept “Effective Time Window”. Along with the observed pulse width modulated resistance, more potential circuit applications can be implemented based on a more realistic memristor switching behaviour.

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

Currently, we have no practical emulation solution for analogue and mixed-signal (AMS) circuits, unlike resolutions found for FPGA digital circuit emulation. This paper presents a high Q crystal oscillator circuit emulation based on Wave Digital Filter (WDF). An analogue circuit emulation method was used based on WDFs proposed in [1] to cover the entire flow of transforming an analogue circuit from a SPICE netlist towards FPGA hardware implementation. Although the WDF has been shown to be effective for circuits with linear elements, a proper method for dealing with nonlinear components, such as MOS transistors, is required. [2] proposed a WDF model for MOS transistors that can solve the connectivity problem in traditional nonlinear WDF models while maintaining analogue emulation accuracy and efficiency. As emulation examples, Resistor-Capacitor (RC), Common Source amplifier (CS), and high Q crystal oscillator circuits were implemented in WDF and compared to their SPICE simulations for verification purposes.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

Emerging memristor-based array architectures have been effectively employed in non-volatile memories and neuro-morphic computing systems due to their density, scalability and capability of storing information. Nonetheless, to demonstrate a practical on-chip memristor-based system, it is essential to have the ability to apply large programming voltage ranges during the characterisation procedures for various memristor technologies. This work presents a 16x16 high voltage memristor characterisation array employing high voltage CMOS circuitry. The proposed system has a maximum programming range of ±22V to allow on-chip electroforming and I-V sweep. In addition, a Kelvin voltage sensing system is implemented to improve the readout accuracy for low memristance measurements. This work addresses the limitation of conventional CMOS-memristor platforms which can only operate at low voltages, thus limiting the characterisation range and integration options of memristor technologies.

The memristor, because of its controllability over a wide dynamic range of resistance, has emerged as a promising device for data storage and analog computation. A major challenge is the accurate measurement of memristance over a wide dynamic range. In this paper, a novel read-out circuit with feedback adjustment is proposed to measure and digitise input current in the range between 20nA and 2mA. The magnitude of the input currents is estimated by a 5-stage logarithmic current-to-voltage amplifier which scales a linear analog-to-digital converter. This way the least significant bit tracks the absolute input magnitude. This circuit is applicable to reading single memristor conductance, and is also preferable in analog computing where read-out accuracy is particularly critical. The circuits have been realized in Bipolar-CMOS-DMOS (BCD) Gen2 technology.

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with ‘memimpedace’ elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at$100^{o}C$across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance’s quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).

In recent years, RRAM technology has been actively developed as a means of reducing power dissipation and area in a host of circuits, most notably artificial neuron synapses. However, further reduction in energy consumption may be possible by transitioning to capacitive synapses and combining them with adiabatic technique. In this work, we present and analyse the function and power dissipation of an artificial neuron with capacitive synapses where the synaptic tree is fed by a regenerative clock. Whilst the weights are fixed in this case, developments into memcapacitor technology offer the promise of tuneability in the future. In our example, a 4-synapse design was used as a proof-of-concept baseline at various frequencies. Our simulation at 1 MHz indicates a æ 91% reduction of energy when using Regenerative Capacitive Synapses vs. standard, nonregenerative ones, which translates into a æ 35% drop in overall artificial neuron energy dissipation. The higher the ratio of synapses/soma, the higher the power savings, which is important for building larger and more complex neurons in silico.

Detecting neuronal activity for rehabilitation/assistive devices is an example of extreme edge computing, featuring stringent requirements for data bandwidth from implantable acquisition system, low-power consumption and ideally also low latency. Recently, we proposed a neural recording system which detects neural spikes directly on the signals collected from electrophysiological probes. The system achieves power efficiency by utilising a combination of integrative sensing and ultra-fine offset compensation. A central component of this design is a memristive load, which is utilised as a trimming device along the differential branches of the core amplifier, ultimately allowing system offset tuning with μν precision. Previous work has assumed that the memristive device features a linear, or nearly-linear current-voltage (IV) characteristic. In this paper, we study the impact of memristor IV non-linearity on the effective gain and offset compensation capability of the system. Results show that the non-linearity experimentally measured from our in-house metal-oxide memristor technology only induces a small gap between nominal resistive state and static RS (as reflected on the IV). This leads to a very small degradation of gain (≈ 2.5%) and offset compensation (≈ 50% increased offset tuning sensitivity), but very crucially proves that introducing IV non-linearity does not materially change either the extreme offset trimming precision or the overall performance. This was the last conceptual bottleneck identified before practical implementation and it has now been overcome.

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

Memristor crossbar arrays offer a novel new approach for designing high density non-volatile memory; however, precise measurement of resistive crossbar elements requires parallel current sensing capability not found in existing instruments. To provide this capability, we have designed and built an FPGA-based crossbar control instrument with independent per-channel biasing and measuring. In this paper, we cover the architecture of this new instrument, its operation and interface, and the results of testing conducted on the instruments pulse driver circuitry.

In this demonstration, we present a new electro-forming process, along with a new instrument to support this procedure. Memristor arrays will be available for the user to electroform, write, and read the resulting resistive state of the devices.

A methodology is introduced here to exploit the programmability of the memristors in order to realize reconfigurable monolithic analogue circuit elements. Classical network synthesis methods are used to synthesize adjustable active inductors with inductance values exceeding those of on-chip passives by several orders of magnitude. In this paper, a wide range of active inductance values are obtained by employing memristor to control the biasing current of operational transconductance amplifiers used to implement gyrators. The gyration constant of the proposed gyrator will be linearly controlled by memristance state. The implementation of the designed circuit is realized in 0.18μm commercially available complementary metal-oxide-semiconductor (CMOS) technology from TSMC. Circuit performance is simulated using Cadence Virtuoso. The utilized off-chip memristor is a metal-oxide bi-layer memristor which exhibits a non-volatile memristance range of 4.7kΩ to 170kΩ. The active inductance range achieved is from approximately 95μH to 1.55mH with an inductive bandwidth of 69MHz and 18MHz respectively. The total power consumption is between 0.21mW to 1.95mW depending on the memristance and equivalent inductance.

A flexible, versatile, and visually rich memristor crossbar simulator is presented in this paper. The system is represented by a Python graphical user interface (GUI) and memristor simulator engine which can instantiate crossbars of any size made out of any available memristor model. This system serves as an education tool, allowing the user to experiment with memristors in a crossbar configuration.

The ability to identify (detect) and categorise (sort) neural spikes in real-time and under highly restrictive power/area budgets is a major enabling technology towards the development of intelligent implantable systems. In this work we propose a memristor-CMOS hybrid architecture concept that relies on a `template pixel' (texel) circuit combining CMOS and memristive devices to perform on-line spike sorting through template matching. We show through simulation how the texel is capable of comparing an input voltage against a stored (in the memristors) value and converting the degree of matching between input and stored pattern into a current. We further illustrate the fundamental texel design space that includes tuning it to a different preferred input voltage and controlling the sharpness of the tuning. Finally, we estimate that even in an unoptimised technology and design a texel array capable of recognising three different 10-point patterns will consume a very promising maximum of 3.15 μW for a footprint of approx. 500 μm2.

We demonstrate a desktop platform which has the ability of fully characterizing RRAM crossbar arrays while not compromising on ease-of-use. The setup consists of our bespoke PCB system connected to a local PC (laptop), on which a Pyhton interface allows the user to directly interact with individual RRAM cells packaged in either crossbar or stand-alone configurations. The platform is capable of current-compliant forming among other exotic pulsing schemes, used for exposing IV and switching characteristics or utilising the devices for a wide range of applications. These operations can be applied on one, or several cells, in an automated fashion, drastically accelerating data acquisition.

A practical system for reading out from linear, multi-level, selectorless Resistive Random Access Memory (RRAM) arrays based on a Trans-Impedance Amplifier (TIA) approach is presented and studied. SPICE simulation of the core of the system is performed in order to extract predicted sensitivity to error factors such as non-zero TIA offsets and access resistance. A physical implementation of the system is then tested on a small, 12 × 12 reference array and measured results show its ability to decode absolute resistive states in the range of 1 kΩ–220 kΩ within ≈ 11% tolerance.

Accurate modeling of memristive devices is a critical condition that will allow the realization of large-scale memristor based circuits. The current methodology regarding modeling focuses on obtaining realistic pinched hysteresis curves, which are memristor signatures, but these do not hold useful information regarding device performance. We divert from this practice and propose a SPICE memristor model constructed based on qualitative verified assumptions of real memristive device operation. Our model introduces volatile effects that render a rate-dependent operation, and also accounts for both bipolar and unipolar switching. We demonstrate its plausibility via a wealth of simulation cases, which are qualitatively similar to several memristor dynamics reported in literature. Finally our model is benchmarked against measured results acquired by solid-state TiO2memristors.

Event-based computation is a well-established way of reducing the complexity of neural modelling, often used as an enabling step towards the simulation of large neuronal ensembles. Recently, the advent of the physical memristor has provided the scientific community with a stand-alone nanoelectronic device that exhibits strongly `synapse-like' behaviour and can be used in general neural modelling. In this paper we review the suitability of the most common, basic memristor models for use in tandem with event-based techniques and conclude that neither of them can support spike timing-dependent plasticity (STDP); a staple of modern neuroscience.We then identify the necessary attributes of any model that can enmesh STDP into event-based computation and present measured results evidencing that solid-state TiO2-based memristors intrinsically support such feature.

We demonstrate a practical application of memristors in a cross-bar memory array. The full set-up consists of only a PC, an mBED microcontroller and a PCB hosting external components and the memristor cross-bar chip. The system can be used for general purpose memory storage, but in this case we use it as a binary image storage device. A MATLAB interface allows the user to load a binary image into the memory and observe the resulting internal memory states of each memristor in the array along with key performance metrics describing the speed and degree of success of the memory `write' operation.

In this paper we present a practical approach to employ solid-state TiO2memristors as tunable loads in filter configurations. First, memristive devices are employed in discrete realizations of tunable active filter topologies. Using an external programming circuit to set the devices to a desired memristive state enables control of the filter's characteristics, namely passband boundaries and quality factor. Utilization of a memristor as a tunable load in low-pass and band-pass filter topologies is then experimentally demonstrated. We further expand this concept by demonstrating an amplitude-controlled gain amplifier topology. In this topology, instead of using external control circuitry to set the memristive state, the state is set internally during operation, providing an automatic gain control.

We present a low pass stepped impedance filter which is based on a single microstrip line of uniform width. The impedance of the line is influenced by the region of the substrate on which the filter section is disposed. A large high-to-low impedance ratio is achieved by application of the Maxwell-Wagner polarization mechanism which results into a colossal effective electric permittivity. This method is competitive to other implementations as it is fully compatible with standard CMOS technologies, exhibits a large attenuation factor in the stop band and results into a compact design.

The paper proposed miniaturized delay lines on layered synthetic substrate materials which support slow-electromagnetic propagation. Under certain conditions such substrates mimic materials with ultra-high electric permittivity. The proposed structure is easily fabricated and a miniaturization factor of two orders of magnitude is reported. Theoretical and experimental results are in good agreement.

The fundamental energy per bit of information created, kTln(2), is given by the theory of thermodynamics. This paper investigates how this limit compares with the energy requirements of an amplifier. The link between bound information and physical energy is shown and a proposal of how information processing occurs in an LNA is made. Current LNA implementations require seven orders of magnitude greater than this limit. This is due to the energy which is required in order to represent the signal at the output of the amplifier to a given resolution and accuracy.

Polar modulation has been adopted by modern wireless systems due to its high power efficiency. In this paper, a novel behavioral model for a digital polar transmitter is presented. The polar transmitter contains an array of amplifiers, which are controlled digitally. A system level simulator is used to model each amplifier. The effects of different number of stages on the mandatory data rates are studied with respect to the error vector magnitude, in conformance to the ultra-wideband standard. Next the complementary cumulative distribution function is studied for a four-stage digital polar transmitter in order to gain an understanding of when each individual stage is turned on. Lastly, nonlinearity, modeled as gain variation for the different parallel stages, is included for a four-stage digital polar transmitter when the data rate is 480 Mbps. Results demonstrate the feasibility of obtaining high efficiency using digital polar transmitters for multiband OFDM UWB systems.

We report an investigation on the feasibility of developing distributed circuit elements and filters using standard complementary metal-oxide-silicon (CMOS) technologies. We propose to exploit the low loss interfacial polarisation propagating modes known to occur on multilayered substrates to realise a high effective substrate dielectric constant. Our approach allows the realisation of physically small but electrically large distributed circuit elements and filters on a standard CMOS substrate without recourse to high K materials

This paper presents a new inductance-capacitance (LC) oscillator topology. The circuit configuration proposed employs a single inductor for the LC resonator tank. The tank is connected to an NMOS cross-coupled pair with PMOS active load. A second NMOS cross-coupled pair is placed between the gates of the active loads to enhance the positive feedback without degrading the phase noise. The technology used for the design is a standard CMOS 0.18mum. Simulations are shown to compare the performance of the proposed topology, in terms of phase noise and power consumption, with the well-known complementary cross-coupled topology and the NMOS cross-coupled topology with active load

A four-channel common-emitter (CE) transimpedance amplifier (TIA) array for optical receiver applications is studied in terms of gain, bandwidth, noise, and crosstalk between adjacent channels. The substrate crosstalk is analyzed by using a proposed lumped-element model. HSPICE simulations were conducted by using a 0.8 /spl mu/m Si/SiGe HBT technology, confirming the small signal analysis and the lumped model for crosstalk analysis. A test chip was fabricated and the measured results will be available shortly.