Modular adders are essential components in finite field arithmetic, serving as key components in public-key cryptographic algorithms like Elliptic Curve Cryptography (ECC) and Post-Quantum Cryptography (PQC). Naïve implementation of modular adders, due to two cascaded adders with large operand bit widths struggle to meet high-frequency requirements. On the other hand, parallel implementations, while faster, demand excessive resources and power, making them impractical for many applications. This paper introduces a novel modular addition algorithm leveraging a novel operand representation based on the two-valued digit encoding (Twit). In this approach, each operand is represented as an n-bit unsigned number augmented by a Twit value {0,±δ}. The algorithm efficiently computes modular addition by speculating and dynamically adjusting the twit value in the result, achieving both computational and resource efficiency. The proposed design has been implemented on a Xilinx 7-series FPGA, demonstrating superior performance in achieving high operating frequencies (i.e., 8% to 36% depending on operand bit widths) while significantly reducing resource utilization (i.e., >36%). In addition to extensive analytical and synthesis-based evaluations, we further demonstrate the benefits of the proposed adder within application-level cryptographic datapaths (ECC and PQC).

Recent studies on integrated circuits interconnections are mainly concentrated on the analysis of crosstalk and delay, by taking the trade-off between accuracy, speed, and complexity into consideration. The new idea of this paper is to apply the convex optimization method to analyze crosstalk and delay of the lossy coupled interconnections in identical and non-identical forms. For this purpose, a simple and comprehensive model is proposed to cover the functional and dynamic crosstalk in a computationally-effective way. More specifically, various case studies are determined to analyze the transient response of the coupled transmission lines with arbitrary excitation sources in the presence of both capacitive and inductive coupling characteristics. To validate the model, the numerical and Advanced Design System (ADS) simulation results are compared to indicate the desired accuracy. The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively. In addition, the computational speed of the proposed method is about twice higher than ADS and HSPICE. The proposed model is extendible to handle${N}$coupled lines, making it appropriate to model complex integrated circuit interconnections.

In this paper, we presented a graph-based computing model to perform the basic arithmetic operations using the DNA computing model with maximum parallelization capabilities. In other words, we proposed a mathematical transformation model to map the basic arithmetic operations to the Hamilton Path Problem (HPP) which can be solved with DNA computers easily and efficiently. Our analyses and simulations show the feasibility and effectivity of the proposed transformation. This technique can open new horizons for performing the general-purpose arithmetic operations with massive parallelism of the DNA strands.

Reverse engineering is a great peril for hardware security especially when functional behavior extraction of the circuit is needed. In this paper a novel method is presented to obfuscate the wiring topology of the design for hindering or even preventing the reverse engineering. In the proposed methodology, new standard cells (Wire Scrambling cells) are presented and then, a physical design methodology is proposed in which wiring topology of the circuit is scrambled automatically using the suggested wire scrambling cells. Experimental results show that reverse engineering can be hindered or even practically protected in cost of negligible overheads in area, power consumption and total wire length.

RF/wireless interconnect is an emerging technology for mitigating the problems of nano-scale metal wires in ultra-large integrated circuits. However, there is no EDA physical design flow for using this technology in conventional application specific ICs. In this paper, an architecture containing both wired and wireless interconnects is presented for regular ASICs corresponding with assignment and placement algorithms for RF-interconnect resources. Experimental results show that total wirelength (routing congestion) and critical delay of attempted benchmarks is reduced by 16.8% and 30.1% on average, respectively. These benefits are earned in the cost of 2.33% area and 11.89% power consumption overhead for large circuits. Moreover, paper concludes that the area and power consumption overheads are lower considerably when the size of design grows.

Architectural advancement in hardware implementation of Java increases the performance. Java processors reduce the overhead of execution time and memory accesses of traditional implementation of JVM in embedded systems. To improve the performance of Java processors and decrease the execution time, we decided to customize a processor is called JOP. We design a Reconfigurable Functional Unit (RFU) which is integrated to JOP's core for executing the Custom Instructions (CIs) that are generated offline. In this article the efficiency of an extensible Java processor is analyzed with the number of clock cycles in several signal processing application benchmarks. Using this architecture, performance is improved by 31.8% in average compared to basic JOP.

In this paper, we propose a multiplexed 3D-switch box architecture that decreases the number of TSVs required for routing with a slight overhead in total wirelength. Our experimental results show that the presented architecture reduces the number of routing TSVs by about 48% in cost of less than 2% wirelength overhead.

In high frequency FPGAs with technology scale shrinking and threshold voltage value decreasing and based on existing large numbers of unused resources, leakage power has a considerable contribution in total power consumption. On the other hand, process variation, as an important challenge in nano-scale technologies, has a great impact on leakage power of FPGAs. Reconfigurability of FPGAs makes an unique opportunity to mitigate these challenges by their unique variation map extraction. In this paper, a per-chip process variation-aware placement (VMAP) algorithm is proposed to reduce the leakage power of FPGAs using the extracted variation map without neglecting dynamic power consumption. VMAP is adaptive to different process variation maps of various FPGA chips. Experimental results on attempted benchmarks show that power-delay-product (PDP) cost is reduced by 7.2% in the VMAP compared with conventional placement algorithms, with less than 16.8% standard deviation for different variation maps.

Asynchronous serial transceivers have been recently used for data multiplexing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the serial transmission but these links have not been exploited in FPGAs yet. In this paper, we present a new architecture corresponding with a routing algorithm to use the asynchronous wire multiplexing technique in FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (9.37% and 9.03%, respectively) by using the asynchronous wire multiplexing without any performance degradation in cost of a little overhead in area and computation time (2% and 0.84%, respectively)

Multi-domain clock skew scheduling is a cost effective technique for performance improvement. However, the required wire length and area overhead due to phase shifters for realizing such clock scheduler may be considerable if registers are placed without considering assigned skews. Focusing on this issue, in this paper, we propose a skew scheduling-aware register placement algorithm that enables clock tree optimization by considering domains assigned to registers in placement. Our experimental results show that the proposed approach remarkably decreases clock wire length and clock network power consumption at the cost of a slight increase in total wire length.

Mis-prediction is a dominant problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in failing the design cycle convergence. In this paper, a new planning methodology is presented in which a masterplan of the chip is constructed in early levels of physical design and the rest of succeeding physical design stags operate considering this masterplan. The proposed planning design flow is used to wire planning and buffer resource planning in order to compare with conventional contributions. Experimental results show the considerable improvements in terms of performance, timing yield and buffer usage.

Interconnect mis-prediction is a dominant problem in nanoscale design that may weaken the quality of physical design algorithms or may even increase the design divergence possibility. In this paper, a new interconnect planning technique is presented based highway-on-chip approach. In this methodology, some highways are planned on chip and the location and amount of resource in highways are gradually determined during the placement process. Experimental results show that by using this technique, performance of the attempted benchmarks is improved by 13.66% on average and timing yield of the attempted circuits is improved by 10.02% on average. It is also shown that the results of this technique become better when the size of circuits grows.

Buffer insertion plays an increasingly critical role on circuit performance and signal integrity especially in deep submicron technologies. Buffer insertion stage is very important for buffering efficiency. Early buffer insertion may cause misestimating due to unknown cell locations whereas buffer insertion after placement may not be very effective because the cell locations are fixed and buffer resources may be distributed inappropriately.In this paper, a buffer planning algorithm for floor-placement design flow is presented which creates a map of buffer requirements in various regions of the design at the floorplanning stage based on the statistical distribution of critical paths and enforces the placer to distribute white spaces with respect to the estimated buffer requirement map.Experimental results show that the proposed method improves the performance of experimented circuits with smaller number of buffers and better power consumption compare to conventional methods. Furthermore, power-delay product has been improved considerably, especially for large circuits with a small growth in CPU time.

Routing congestion is a critical issue in deep submicron design technology and it becomes one of the most challenging problems in today's design flow. This paper presents a true probabilistic congestion prediction method based on router's intelligence to be used in the placement stage of physical design flow. Experimental results show that for IBM-PLACE benchmarks, our prediction algorithm estimates the congestion more accurately than a recent method by about 19%. Furthermore, a new congestion reduction algorithm is presented which is based on contour plotting. Our experiments show that our algorithm reduces congestion by about 28% on average. In addition, comparing our results with a recent approach shows that our reduction technique reduces congestion more by about 13%.

The recent growth of cellular phone systems, voice over IP devices, and other multimedia applications has created a considerable need for efficient voice coding algorithms. These algorithms usually require intensive amount of signal processing capabilities and demand significant signal processing power. The current market trend of integrating multiple voice channels into a single die has further intensified the need for more powerful hardware platforms. Some new design ideas such as vocoder-specialized DSP architectures, combined RISC/DSP platforms, and adding hardware accelerators or coprocessors to the general-purpose processors have been proposed. In this paper, a new hardware accelerator design has been proposed which executes macro instructions (MIs). The proposed coprocessor can be added to each processor type that can support at least one coprocessor without modifying the compiler and redesigning the processor. It can handle computationally intensive loops in speech coding algorithms parallel with the main processor. The coprocessor along with software optimization reduces clock cycles required for G.723.1 by 80% and G.729 by 64% while MIPS R3000 RISC is used as the host.

This paper presents an area efficient, low-power and robust ACS unit for Viterbi decoder in two synchronous and asynchronous architectures. The asynchronous design is based upon quasi delay insensitive (QDI) timing model which leads to a robust and low power purpose and synchronous architecture uses a hybrid CMOS-pseudo NMOS technology to improve area and throughput factors. Some optimization techniques to reduce the power and area are applied to each design. The simulation results show the asynchronous design has the lowest power consumption with 6.65mW and hybrid CMOS has the lowest transistor counts with 759 in relative to other reported circuits.