AI/ML systems have been deployed in both SoC design/architecture as well as in semiconductor manufacturing over the years. These systems have been independent of each other with process design kits (PDK) being the interface between design and manufacturing. Recent advances in packaging technology and the adoption of chiplet architecture has opened exciting avenues for merged AI/ML systems that bring SoC architecture and manufacturing together. This work explores this opportunity of enabling an AI/ML system that brings manufacturing and design information together for chiplet architecture exploration

Statistical circuit simulation is exhibiting increasing importance for circuit design under process variations. It has been widely used throughout the design of standard cell circuits (SRAM, Flip-Flop, etc.) to maximize yield, i.e. to minimize the failure probability. Existing approaches cannot effectively analyze the failure probability when failed samples are distributed in multiple disjoint regions, nor handle the circuits with a large number of variations. To tackle these challenges, the proposed hyperspherical clustering and sampling (HSCS) approach first identifies multiple failure regions through a reweighted spherical k-means algorithm, which clusters failed samples on a set of hyperspheres, rather than the high dimensional open space. Next, a modified mixture importance sampling is designed to draw samples at those clusters to achieve multiple failure region coverage. The proposed HSCS is evaluated using both mathematical and circuit-based examples. It achieves about 3-order speedup over Monte Carlo with the same level of accuracy, while other importance sampling based approaches either fail to converge or converge to wrong results. Furthermore, HSCS demonstrates excellent robustness by generating consistent results in multiple replications.

The authors present a frequency domain current macro-modeling technique for capturing the dependence of the block current waveform on its input vectors. The macro model is based on estimating the discrete cosine transform (DCT) of the current waveform and then taking the inverse transform to estimate the time domain current waveform. The DCT of a current waveform is very regular and closely resembles the DCT of a triangular or a trapezoidal wave. The authors use this fact and the relation between the DCT, discrete Fourier transform (DFT), discrete time Fourier transform (DTFT), and the Fourier transform (FT) to infer the template functions for the current macro model. These template functions are characterized by using various parameters like amplitude, phase decay factor, time period, etc. These parameters are modeled as functions of the input vector pair using regression. Regression is done on a set of current waveforms generated for each circuit using HSPICE. These template functions are used in an automatic characterization process to generate current macro models for various CMOS combinational circuits.

We present a frequency domain current macro-modeling technique for capturing the dependence of the block current waveform on its input vectors. The macro-model is based on estimating the Discrete Cosine Transform (DCT) of the current waveform as a function of input vector pair and then taking the inverse transform to estimate the time domain current waveform. The input vector pairs are partitioned according to Hamming distance and a current macro-model is built for each Hamming distance using regression. Regression is done on a set of current waveforms generated for each circuit, using HSPICE. The average relative error in peak current estimation using the current macro-model is less than 20%.

In order to perform block level analysis of the on-chip power distribution network, a high-level model is required that captures the dependence of the current waveform drawn by a logic block, per cycle, on its input vector pair. We present a frequency domain macro-modeling technique for capturing this dependence. The macro-model is based on estimating the Discrete Cosine Transform (DCT) of the current waveform and then taking the inverse transform to estimate the time domain current waveform.

We present a novel technique for estimating individual wire lengths in a given standard-cell-based design during the technology mapping phase of logic synthesis. The proposed method is based on creating a black box model of the place and route tool as a function of a number of parameters, which are all available before layout. The place and route tool is characterized, only once, by applying it to a set of typical designs in a certain technology. We also propose a net bounding box estimation technique based on the layout style and net neighborhood analysis. We show that there is inherent variability in wire lengths obtained using commercially available place and route tools-wire length estimation error cannot be any smaller than a lower limit due to this variability. The proposed model works well within these variability limitations.