An effective clock-skew scheduling scheme in the high-level synthesis process targeted for power and speed optimization is presented. The proposed scheme has the following distinctive features: 1) a clock-skew management algorithm that selects a minimum set of clock phases to achieve the optimization goals is developed; 2) the effect of module binding in high-level synthesis was not considered in previous studies, which may lead to designs with timing violation; a discussion on how to model the effect of module binding is provided; 3) a heuristic low-power module binding algorithm that provides near-optimal results quickly is proposed; and 4) a technique called reallocation is proposed to exploit all available skews and thus maximize the capability of clock-skew scheduling. Experimental results show that, on the average, 48% power reduction is achieved by the proposed method. At most five clock phases are required, while in most cases two to four clock phases are sufficient.

High temperature in test process may invalidate a test due to extra delay, or even damage the circuit under test. Therefore, a thermal-safe test can avoid undesirable yield loss due to the extra delay induced by high temperature. Traditional high level test synthesis approaches just improve hierarchical testability of circuits and minimize test application time. If the thermal effects are ignored, the higher test power density may produce unacceptable high temperature even though thermal management is carried out in the functional mode. Since the thermal-aware design cannot achieve thermal-safe hierarchical testing, a thermal-safe high level test synthesis approach is proposed in this paper to deal with this problem. In the proposed test synthesis procedure, the given temperature constraints will be satisfied in the test environment construction process. Experimental results show that the proposed test synthesis method can provide thermal-safe hierarchical test and shorten test application time compared to conventional high-level test synthesis approaches.

A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay-fault coverage is usually attributed to the fact that a two-pattern test for delay testing cannot be delivered to modules under test in two consecutive cycles. To solve the problem, we propose an HLTS method that ensures that valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in modules; in contrast, the fault coverage in circuits synthesized by a left-edge-algorithm-based allocation algorithm is rather poor. The area overhead due to this method ranges from 1% to 10% for 16-b datapath circuits. On the other hand, hierarchical test patterns cannot provide good delay-fault coverage for faults in interconnection structure and registers. The reason is that some control sequences required for delay-fault detection cannot be provided by the controller. We propose two design-for-testability insertion methods to deal with this problem. Experimental results show that, on the average, at least 11% higher delay-fault coverage is achieved by these methods.

A high-level test synthesis (HUTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embedded modules, guarantees 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay fault coverage is usually attributed to the fact that two-pattern test for delay testing cannot be delivered to modules under test in consecutive cycles. To solve the problem, the paper proposed an HUTS method that ensures valid test pairs can be sent to each module through synthesized circuit hierarchy. Experimental results show that this method achieves 100% fault coverage for transition faults in functional units, while the fault coverage in circuits synthesized by LEA-based allocation algorithm is rather poor. The area overhead due to this method ranges from 2% to 10% for 16-bit datapaths