EDBT 2026 Demo / reviewers in the wild / expert
Hendrik A. Goosen
dblp:00/4319
· DBLP profile ↗
4ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 2Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Memory systems · 38% Performance modeling and evaluation · 20% Parallel and multicore computing · 20% |
Topics — the 13 heaviest of 13, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation › performance analysis tools
performance visualization |
0.0 | 1 | 1994 | Chiron parallel program performance visualization system · Comput. Aided Des. 1994 |
Memory systems › memory hierarchy
cache hierarchy |
0.0 | 1 | 1989 | Multi-level Shared Caching Techniques for Scalability in VMP-M/C · ISCA 1989 |
Electronic design automation › hardware verification and test
concurrent checking |
0.0 | 1 | 1989 | The Byzantine hardware fault model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 |
Memory systems › shared memory
distributed shared memory |
0.0 | 1 | 1989 | Multi-level Shared Caching Techniques for Scalability in VMP-M/C · ISCA 1989 |
Electronic design automation › hardware verification and test
fault modeling |
0.0 | 1 | 1989 | The Byzantine hardware fault model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 |
Parallel and multicore computing › multiprocessor system
scalable multiprocessor |
0.0 | 1 | 1989 | Multi-level Shared Caching Techniques for Scalability in VMP-M/C · ISCA 1989 |
Memory systems › cache › multiprocessor cache
shared cache |
0.0 | 1 | 1989 | Multi-level Shared Caching Techniques for Scalability in VMP-M/C · ISCA 1989 |
Processor architecture and microarchitecture › multiprocessor architecture
bus-based multiprocessor |
0.0 | 1 | 1988 | The VMP Multiprocessor: Initial Experience, Refinements and Performance Evlauation · ISCA 1988 |
Memory systems
cache coherence |
0.0 | 1 | 1988 | The VMP Multiprocessor: Initial Experience, Refinements and Performance Evlauation · ISCA 1988 |
Parallel and multicore computing
multiprocessor system |
0.0 | 1 | 1988 | The VMP Multiprocessor: Initial Experience, Refinements and Performance Evlauation · ISCA 1988 |
Memory systems › cache management
software-managed cache |
0.0 | 1 | 1988 | The VMP Multiprocessor: Initial Experience, Refinements and Performance Evlauation · ISCA 1988 |
Parallel and multicore computing › parallel computing
parallel application performance |
0.0 | 1 | 1994 | Chiron parallel program performance visualization system · Comput. Aided Des. 1994 |
Performance modeling and evaluation › simulation › discrete-event simulation
trace-driven simulation |
0.0 | 2 | 1989 | Multi-level Shared Caching Techniques for Scalability in VMP-M/C · ISCA 1989 The VMP Multiprocessor: Initial Experience, Refinements and Performance Evlauation · ISCA 1988 |
Methods — techniques the papers use, named apart from their topics
trace-driven simulation · 0.0shared caching · 0.0fault model analysis · 0.0software cache management · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | Chiron parallel program performance visualization system
Hendrik A. Goosen, Anna R. Karlin, David R. Cheriton, Dieter Polzin |
Comput. Aided Des. | 1 |
| 1989 | Multi-level Shared Caching Techniques for Scalability in VMP-M/CabstractThe problem of building a scalable shared memory multiprocessor can be reduced to that of building a scalable memory hierarchy, assuming interprocessor communication is handled by the memory system. In this paper, we describe the VMP-MC design, a distributed parallel multi-computer based on the VMP multiprocessor design, that is intended to provide a set of building blocks for configuring machines from one to several thousand processors. VMP-MC uses a memory hierarchy based on shared caches, ranging from on- chip caches to board-level caches connected by busses to, at the bottom, a high-speed fiber optic ring. In addition to describing the building block components of this architecture, we identify the key performance issues associated with the design and provide performance evaluation of these issues using trace-drive simulation and measurements from the VMP. This work was sponsored in part by the Defense Advanced Re- search Projects Agency under Contract N00014-88-K-0619. David R. Cheriton, Hendrik A. Goosen, Patrick D. Boyle |
ISCA | 2 |
| 1989 | The Byzantine hardware fault modelabstractA new fault model for temporary failures is presented. This model is motivated and supported by recent experimental studies on types of temporary failures which cannot be explained by existing models. This new fault is called a Byzantine fault by analogy with the well-known Byzantine Generals problem in distributed systems. An example of an important type of Byzantine fault called a short transient is analyzed. The effects of Byzantine faults on concurrent error checking circuits are discussed. Design techniques to eliminate the effects of Byzantine faults are presented.> Takashi Nanya, Hendrik A. Goosen |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 1988 | The VMP Multiprocessor: Initial Experience, Refinements and Performance EvlauationabstractVMP is an experimental multiprocessor being developed at Stanford University, suitable for high-performance workstations and server machines. Its primary novelty lies in the use of software management of the per-processor caches and the design decisions in the cache and bus that make this approach feasible. The design and some uniprocessor trace-driven simulations indicating its performance have been reported previously. Initial experience with the VMP design, based on a running prototype as well as various refinements to the design, is presented. Performance evaluation is based both on measurement of actual execution as well as trace-driven simulation of multiprocessor executions from the Mach operating system.> David R. Cheriton, Anoop Gupta, Patrick D. Boyle, Hendrik A. Goosen |
ISCA | 4 |