EDBT 2026 Demo / reviewers in the wild / expert

Bruno Franzini

dblp:00/4371 · DBLP profile ↗
← Back
3ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 83% Integrated circuit design · 17%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
timing analysis		 0.021997
Accurate and Efficient Macromodel of Submicron Digital Standard Cells · DAC 1997
An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells · DAC 1995
Electronic design automation › circuit modeling
timing characterization		 0.021997
An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells · DAC 1995
Accurate and Efficient Macromodel of Submicron Digital Standard Cells · DAC 1997
Electronic design automation › timing analysis › delay modeling
gate delay modeling		 0.011997
Accurate and Efficient Macromodel of Submicron Digital Standard Cells · DAC 1997
Integrated circuit design › VLSI design
standard cell library		 0.011995
An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells · DAC 1995

Methods — techniques the papers use, named apart from their topics

statistical worst-case analysis · 0.0assigned probability technique · 0.0
YearPublicationVenuePosition
1997 Accurate and Efficient Macromodel of Submicron Digital Standard Cells
abstract
In this paper a new analytic gate delay modelingtechnique is presented that allows to accuratelyreproduce the timing behavior of deep submicron digitalstandard cells for a large range of operating conditions.The proposed technique sensibly improves the accuracyof the existing analytic delay models and it usuallyrequires less simulations for the cell characterization.Moreover it is compatible with the most advanced interconnectdelay models that have been recently proposed inthe literature.
Cristiano Forzan, Bruno Franzini, Carlo Guardiani
 DAC2
1996 Manufacturability of low power CMOS technology solutions
abstract
This paper discusses manufacturabilty of state-of-the-art low power technologies.We report the results on two generations of bulk CMOS technologies, triple-well CMOS and Thin Film Silicon on Insulator (TFSOI) technologies.We present technology capabilities for several values of supply voltage and address the issue of performance scaling with the supply voltage reduction.Then we focus on the statistical characterization of these technologies and discuss both interchip and intrachip variations.Finally, we present the digital and analog designer perspectives on the low power IC operation.
Andrzej J. Strojwas, Michele Quarantelli, J. Borel, Carlo Guardiani, Germano Nicollini, G. Crisenza, Bruno Franzini, J. Wiart
 ISLPED7
1995 An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells
abstract
The possibility of determining the accurate worstcase timing performance of a library of standard cells is of great importance in a modern VLSI structured semicustom IC design flow. The margin for profitability is indeed extremely tight because of the ever increasing performance demand which can hardly be satisfied by a corresponding progress of the process technology. It is therefore of utmost importance to avoid excessively pessimistic estimates of the actual cell performance in order to exploit all the potential of the fabrication process. In this paper it is described a technique that allows to determine the worst-case points with an assigned probability value. It is thus possible to select the desired level of confidence for the worst-case evaluation of digital IC designs with good accuracy. The results of the Assigned Probability Technique (APT) are presented and compared with those obtained by standard methods both at cell and at circuit level showing the considerable benefits of the new method.
Alessandro Dal Fabbro, Bruno Franzini, Luigi Croce, Carlo Guardiani
 DAC2