We address the problem of partitioning a technology mapped FPGA circuit onto multiple FPGAs of a specific target technology.The physical characteristics of the multiple FPGA system (MFS) pose additional constraints to the circuit partitioning algorithms: the capacity of each FPGA, the timing constraints, the number of I/ Os per FPGA, and the pre-designed interconnection patterns of the MFS.Existing partitioning techniques which minimize just the cut sizes of partitions fail to satisfy the above challenges.We therefore present a rectilinear partitioning algorithm which efficiently and accurately handles timing specifications.The signal path delays are estimated during partitioning using a timing model specific to a multiple FPGA architecture.The model combines all possible delay factors in a system with multiple FPGA chips of a target technology.A new dynamic net-weighting scheme was incorporated to minimize the number of pin-outs for each chip.Finally, we have developed a graph-based global router for pin assignment which can handle the pre-routed connections of our MFS structure.We successfully partitioned the MCNC Xilinx FPGA benchmarks producing 100% routable designs with high utilization levels in all cases.Using the performance optimization capabilities in our approach we have successfully partitioned these benchmarks satisfying the critical path constraints and achieving a significant reduction in the longest path delay.An average reduction of 17% in the longest path delay was achieved at the cost of 5% in total wire length.We have proved the effectiveness of our performance optimization technique by verifying the timing predictions of our partitioner with the actual delays obtained after placement and routing of a partitioned MFS.Partitioning results obtained with the Xilinx mapped MCNC benchmarks are encouraging.