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Michael Payer

dblp:00/4828 · DBLP profile ↗
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8ranked-venue papers
2as first author
0since 2021 · last 1995
0000-0003-4469-8335ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › model checking
hardware model checking		 0.011995
Model Checking in Industrial Hardware Design · DAC 1995
Electronic design automation
hardware verification and test		 0.011995
Model Checking in Industrial Hardware Design · DAC 1995
Electronic design automation › high-level synthesis
data path synthesis		 0.011991
Data-Path Synthesis Using Path Analysis · DAC 1991
Electronic design automation
high-level synthesis		 0.011991
Data-Path Synthesis Using Path Analysis · DAC 1991

Methods — techniques the papers use, named apart from their topics

model checking · 0.0abstraction · 0.0path analysis · 0.0
YearPublicationVenuePosition
1995 Model Checking in Industrial Hardware Design
abstract
This paper describes how model checking has been integrated into an industrial hardware design process. We present an application oriented specification language for assumption/commitment style properties and an abstraction algorithm that generates an intuitive and efficient representation of synchronous circuits. These approaches are embedded in our Circuit Verification Environment CVE. They are demonstrated on two industrial applications.
Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl
 DAC3
1993 The Siemens high-level synthesis system CALLAS
abstract
In this paper we present the Siemens high-level synthesis system CALLAS and describe its design methodology and synthesis strategy. It supports the synthesis of control-dominated applications and uses a VHDL subset for the algorithmic specification. Its main feature can be characterized as "What you simulate is what you synthesize." This principle permits a validation of the synthesis results by simulation or even formal verification. CALLAS has been successfully applied on real designs which were implemented in silicon. These examples demonstrate that CALLAS fulfils the constraints and objectives of a hardware designer. The circuits are comparable in quality to results achieved by synthesis starting at the register-transfer-level.>
Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy
 IEEE Trans. Very Large Scale Integr. Syst.6
1992 Allocation algorithms based on path analysis
Reinaldo A. Bergamaschi, Raúl Camposano, Michael Payer
 Integr.3
1991 Data-Path Synthesis Using Path Analysis
abstract
Article Data-path synthesis using path analysis Share on Authors: Reinaldo A. Bergamaschi IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y. IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y.View Profile , Raul Camposano IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y. IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y.View Profile , Michael Payer IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y. IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y.View Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 591–596https://doi.org/10.1145/127601.127738Published:01 June 1991 16citation237DownloadsMetricsTotal Citations16Total Downloads237Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
Reinaldo A. Bergamaschi, Raúl Camposano, Michael Payer
 DAC3
1991 Scheduling under resource constraints and module assignment
Reinaldo A. Bergamaschi, Raúl Camposano, Michael Payer
 Integr.3
1991 Partitioning and ordering of CMOS circuits for switch level analysis
Michael Payer
 Integr.1
1988 A system for estimation of numerical stability for matrix operations in systolic arrays
Reinhard Rauscher, Peter Kückendahl, Michael Payer
 Microprocess. Microprogramming3
1987 Verification and validation of hierarchical CMOS gate array layouts
Michael Payer
 Microprocess. Microprogramming1