An accurate metric for the time step control in the power device transient simulation is proposed. This metric contains an exponential term of the dominant time constant of the whole device structure derived from the matrix exponential term of the linearized device state equation. The proposed metric allows larger time step widths than the conventional metric of second order approximation of the local truncation error. It focuses on the dominant part of the transient response and its truncation error approximation is more accurate. In the transient device simulation, box integration method and backward Euler method are used for spatial and temporal discretization, respectively. The discretized nonlinear device equations are solved by using Newton iteration whose initial guess is given by the approximated solution of the linearized device state equation by using the dominant time constant. Total calculation time of the transient simulation of a silicon power DMOSFET by using the proposed method decreases down to 27% of that by the conventional method with keeping the current accuracy of the dominant transient response.

A Dual-mode baseband (W-CDMA/HSDPA and GSM/GPRS/EDGE) and multimedia application processor SoC is described. The SoC fabricated in triple-Vth 65nm CMOS has 3 CPU cores and 20 separate power domains to achieve both high performance and low power. The SoC adopts the Partial Clock Activation scheme that reduces power by 42% for long-time music replay. The IP-MMU is introduced to reduce maximum memory footprint by 43MB, sharing external memory among CPUs and HW-IPs using virtual address space that enables reuse of physically fragmented memory.