EDBT 2026 Demo / reviewers in the wild / expert
Cyril J. Tunis
dblp:00/5155
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 1968
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 69% Storage systems · 19% Integrated circuit design · 12% | |
| Artificial intelligence
1 paper |
Learning paradigms · 50% Optimization for machine learning · 50% | |
| Theoretical computer science
1 paper |
Mathematical optimization · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Optimization for machine learning
adaptive algorithm |
0.0 | 1 | 1967 | An Experimental Investigation of a Nonsupervised Adaptive Algorithm · IEEE Trans. Electron. Comput. 1967 |
Machine learning › Learning paradigms
unsupervised learning |
0.0 | 1 | 1967 | An Experimental Investigation of a Nonsupervised Adaptive Algorithm · IEEE Trans. Electron. Comput. 1967 |
Memory systems › emerging memory technologies
analog memory |
0.0 | 1 | 1968 | A High-Speed Threshold Memory Element · IEEE Trans. Computers 1968 |
Memory systems
memory architecture |
0.0 | 1 | 1963 | A Delay-Line Push-Down List · IEEE Trans. Electron. Comput. 1963 |
Storage systems
storage devices |
0.0 | 1 | 1963 | A Delay-Line Push-Down List · IEEE Trans. Electron. Comput. 1963 |
Memory systems
magnetic core memory |
0.0 | 1 | 1968 | A High-Speed Threshold Memory Element · IEEE Trans. Computers 1968 |
Integrated circuit design › memory circuit design
memory elements |
0.0 | 1 | 1968 | A High-Speed Threshold Memory Element · IEEE Trans. Computers 1968 |
Mathematical optimization › online optimization
adaptive algorithms |
0.0 | 1 | 1967 | An Experimental Investigation of a Nonsupervised Adaptive Algorithm · IEEE Trans. Electron. Comput. 1967 |
Methods — techniques the papers use, named apart from their topics
threshold switching · 0.0nonsupervised adaptive algorithm · 0.0microwave coupling · 0.0delay line storage · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1968 | A High-Speed Threshold Memory ElementabstractAbstract—This note describes a new analog-memory or variable- weight device that can be set to any of 100 stable states and switched between states in 100 ns or less. The device uses the coupling between a circularly polarized microwave signal (as generated by a helical structure) and a partially switched ferrite core. Rodger L. Gamblin, Cyril J. Tunis |
IEEE Trans. Computers | 2 |
| 1967 | An Experimental Investigation of a Nonsupervised Adaptive Algorithm
E. R. Ide, Cyril J. Tunis |
IEEE Trans. Electron. Comput. | 2 |
| 1965 | Linearly Separable Codes for Adaptive Threshold NetworksabstractThe significance of the coding assignment in linear threshold networks used for pattern recognition has been discussed. A heuristic procedure for generating linearly separable codes for a sample set of patterns has been outlined. Experimental results showing the recognition performance of codes so chosen have been shown. The performance of these codes is comparable to the 1-out-of-n code commonly used, but more optimum codes may exist. More work on the coding assignment problem is in order and should allow more efficient linear threshold networks in the pattern recognition application. C. E. Kiessling, Cyril J. Tunis |
IEEE Trans. Electron. Comput. | 2 |
| 1963 | A Delay-Line Push-Down Listabstract``List structure'' arrangements of information are increasingly being used in digital data-processing applications. A ``push-down'' list is one manipulated in a last-in, first-out manner. The implementation of such a list structure is possible in a variety of ways. This paper describes one such method which uses a delay line as a storage device. P. A. Lord, Cyril J. Tunis, H. L. Witter |
IEEE Trans. Electron. Comput. | 2 |