With the latest gaming systems such as X-box, Playstation 3, PSP, IPTV, and H264 requiring more bandwidth, packaged in smaller devices, and providing higher quality, in return they evacuate more heat and consume more power, thus making power consumption and thermal dissipation a major issue for chip designers in the nanometer era.Thermal effects on the chip and package is the next wave. First, there was signal integrity. Then power integrity and now, there is a new first-order effect in the horizon for IC and system designers called thermal integrity. And the traditional design methodology of using uniform temperature across the chip is becoming woefully inadequate and provides insufficient data to the package and system designers, unable to meet the requirement and demands of the consumer. To better understand the impact of temperature variation on chip's performance, both power distribution and package characteristics must be considered in the design and analysis flow. Likewise, a realistic view of the heat distribution across the chip is becoming essential for package and system designers. What makes the analysis of signal, power, and thermal integrity effects challenging is that they must all be considered concurrently across the entire chip, which requires novel approaches to mitigate the issue.The panel will discuss how urgent is the impact of thermal integrity on system designs and is this a real concern or are we making it up?When and under what condition will it become urgent, and is it related to process nodes, low power applications, type of packaging used, etc.? Is there specific design techniques used for more specific multimedia processing? Can you separate the IC design from package and system designs with some assumptions or is co-design the only way? How accurate is the industry's understanding of the physics of the chip (device), interconnect, and package? Is thermal integrity a first order or second order effect?Given the other variations from nominal, how important is this.The moderator will conclude with a summary of the panelist comments and be able to make a forward-looking statement about the future of power and heat and their impact on system design.

The ever-increasing power consumption and packaging density of integrated systems creates on-chip temperatures and gradients that can have a substantial impact on performance and reliability. While it is conceptually understood that a thermal equivalent circuit can be constructed to characterize the temperature gradients across the chip, direct and iterative solutions of the corresponding three-dimensional (3-D) equations are often intractable for a full-chip analysis. Integrated circuit (IC)-specific multigrid (MG) techniques for fast chip level thermal steady-state and transient simulation are proposed. This approach avoids an explicit construction of the matrix problem that is intractable for most full-chip problems. Specific MG treatments are proposed to cope with the strong anisotropy of the full-chip thermal problem that is created by the vast difference in material thermal properties and chip geometries. Importantly, this paper demonstrates that only with careful thermal modeling assumptions and appropriate choices for grid hierarchy, MG operators, and smoothing steps across grid points can a full-chip thermal problem be accurately and efficiently analyzed. This paper further speeds up the large thermal transient simulations by incorporating reduced-order thermal models that can be efficiently extracted under the same MG framework. The experiments carried out in this work have shown that the proposed methodology provides sufficient efficiency in both runtime and memory usage.

The ever-increasing power consumption and packaging density of integrated systems creates on-chip temperatures and gradients that can have a substantial impact on performance and reliability. While it is conceptually understood that a thermal equivalent circuit can be constructed to characterize the temperature gradients across the chip, direct and iterative solutions of the corresponding 3D equations are often intractable for a full-chip analysis. Multigrid accelerated iterative methods can be applied to solve the equivalent circuit problem that is provably symmetric positive definite; however, explicitly building the matrix problem is intractable for most full-chip problems. In This work we present a multigrid iterative approach for the full-chip thermal analysis which does not require explicit construction of the equivalent circuit matrix. We propose specific multigrid treatments to cope with the strong anisotropy of the full-chip thermal problem that is created by the vast difference in material thermal properties and chip geometries. Importantly, we demonstrate that only with careful thermal modeling assumptions and appropriate choices for grid hierarchy, multigrid operators and smoothing steps across grid points, can we accurately and efficiently analyze a full-chip thermal problem. Experimental results demonstrate the efficacy of the proposed multigrid methodology. Our prototyped thermal simulator is able to solve a steady-state problem with more than 10 million unknowns in 125 CPU seconds with a peak memory usage of 231 mega bytes.

With geometries shrinking in nanometer technologies, crosstalk noise becomes a critical issue. Modern designs like system-on-chips have millions of noise-prone nodes, mandating fast yet accurate crosstalk noise analysis techniques. Using linear circuit model, static noise analysis can efficiently estimate crosstalk noise. Traditionally in static noise analysis, drivers' holding resistances are precharacterized without considering the potential impact of crosstalk noise. However, crosstalk induced voltage fluctuation strongly affects the behavior of nonlinear drivers. When facing different coupling interconnects and hence crosstalk noise, a driver's holding resistance can change dramatically. In nanometer circuits, this substantial variation of nonlinear drivers cannot be totally ignored. To achieve high-quality in noise estimation yet maintain the efficiency of linear circuit model, we propose a novel interconnect coupling-aware driver modeling method. Based on layout-extracted interconnect parameters and precharacterized driver models, an effective holding resistance is calculated to capture the impact of the nonlinear driver. Multiple aggressors with synchronous and asynchronous switching activities are also considered. The proposed method is simple, efficient, and enables on-the-fly calculation of the effective holding resistance. Experiments show that with negligible computation overhead, the coupling-aware driver modeling methodology can significantly improve the quality of static noise analysis.