It is well known that the performance of current-steering D/A converters (DACs) is affected by parasitic effects such as static device mismatch and dynamic timing mismatch. Typically, this results into about 10-bit peak performance. To increase this number, the designer has two options: either use a very large silicon area to obtain better matching, or alternatively use a (sophisticated) calibration technique. In this paper we present a D/A converter circuit with a “Redundant Signed Digit” (RSD) coding scheme for binary weighted D/A conversion. This scheme does not really improve the peak performance for full-scale input signals. E.g with a full-scale 3.2 MHz 14-bit input sinusoidal signal, the SFDR equals 60 dB for our circuit. But the performance is only gradually reduced for small input signals: for a -43 dB 14-bit input signal the SFDR is still 44 dB, which is close to the performance of an ideal 14-bit D/A converter. The analog section of this circuit was implemented in a standard 0.18 m (1P6M) CMOS process and requires only 0.1 mm2of silicon area.

The accuracy of high-speed DAC's is limited by dynamic effects such as glitches. Here, a digital calibration technique to compensate this effect is presented. Because of the digital approach, this solution can not be an exact correction of the phenomenon, but band limited attenuation. The approach consists of adding a (digital) compensation signal to correct the glitch. Both a 2-tap and a 4-tap correction are investigated and it is shown that they can greatly reduce spurs over a bandwidth of 30% and 60% of the Nyquist band respectively, provided the glitch energy is known. Next, it is shown how an adaptive calibration with an additional low-speed calibration ADC can be used to estimate the glitch energy. Simulations confirm that the spectral performance can be greatly improved this way.

ΣΔ force-feedback loops have to deal with a stability problem due to phase-lag occurring in the sensor. To tackle this problem traditionally a compensator is introduced in the loop. We show that this traditional approach imposes a constraint on the realizable NTF such that the NTF cannot be optimized. Next we propose a novel unconstrained architecture that allows to implement any NTF. This way greatly improved quantisation noise shaping can be obtained. In a typical design example the improvement was 12 dB.

QuadratureΣΔADCs require a feedback path for both the I and the Q part of the complex feedback signal. A complex DAC could give this feedback with near-perfect I/Q balance. Still, the mismatch between the unit elements of the complex DAC introduces mismatch noise that should be shaped out of the signal band with dynamic element-matching (DEM) techniques. In literature, only quadrature DEM techniques for 3-state (I, Q, 0) unit elements are considered. However, in fully differential circuit, also 5-state unit elements are available. In this case, each unit element can be selected ±1, ±Q or 0. When using these 5-state unit elements, the amount of hardware and power consumption can be reduced significantly. In this paper it is shown how the tree structure, the data directed swapper and the vector quantizer structure can be adapted for the use in fully differential circuits with such 5-state unit elements.

In this paper we propose a way to design continuous time SigmaDelta modulators. The method is based on the Nyquist stability criterion. Based on this criterion we propose to use the vector gain margin as a robust stability margin. Using this margin as a design criterion we design a robustly stable modulator. Finally, we also show how this margin can be used to evaluate the relative stability of a designed modulator

Quadrature SigmaDelta ADCs require a feedback path for both the I and the Q part of the complex feedback signal. If two separated multibit feedback DACs are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an unbalance between the I and Q DAC. This paper proposes a new quadrature bandpass mismatch shaping technique. In our approach the I and Q DACs are merged into one complex DAC, which leads to near-perfect I/Q balance. To select the unit DAC elements of the complex, multibit DAC, the well-known tree structured element selection logic is generalized toward a complex structure and necessary conditions for its correct operation are derived. Finally, a very efficient first-order quadrature shaper implementation is proposed and simulations show the effectiveness of the quadrature bandpass mismatch shaping technique

A powerful technique (multiple storage multi-trees) for storage of geometrical data in CAD applications is presented. A significant improvement has been obtained in the field of region query performance. Memory requirements are slightly lower than for R.L. Brown's well-known multiple storage quadtrees (ibid., vol.5, no.3, p.413-9, 1986). Experimental results for the new data structure are presented. The method may prove to be very useful for VLSI design tools.>

A data structure is presented for the storage of graphical information. It is a modified multiple storage quad tree, with four lists in each leaf quad. A substantial improvement is obtained for region queries, in particular on large windows, and for tree traversal. On the other hand, only an insignificant increase of memory requirement is noticed in particular situations. The method is not complicated, so it can easily be programmed.>

Performance prediction of multiple-storage quad trees is treated. Using random graphical data models, expected values of essential parameters such as the number of internal nodes, the number of object references, and the number of lists are estimated. From these results, more practical characteristics such as memory usage and the speed of windowing operations are obtained. The accuracy of the approximations is evaluated on experimental data.>