International audience

The quest for reliable testing of analogue and mixed-signal circuits remains a cornerstone in the advancement of integrated circuit technology, driving innovation in high-stakes areas such as aerospace and automotive systems. The continuous nature of the signals and the variability of the components make the task both time consuming and difficult to automate. This work presents a general methodology to detect parametric faults in analogue circuits using machine learning models combined with Monte Carlo simulations, advanced signal transformations and optimal classifier selection. The proposed framework is adaptable to different circuit architectures, as demonstrated by simulations of RLC bandpass filters and Sallen-Key filters. In particular, our approach incorporates new metrics that balance classification accuracy with implementation complexity and computational efficiency, providing a scalable solution adapted for automation and integration into an embedded test environment.

As PDL has been developed to be syntactically compatible with TCL, it is possible to use an interpreter to enhance test routines with programming features, such as variables, flow control, etc.. Moreover, one of the big novelties of IEEE 1687 is the native support of interactive behaviour thanks to the PDL-1 instruction set. which allows data read from the target system to be returned to TCL Interpreter. However, it is not quite clear what “Interactive behaviour” actually means and how it gets from simulation to automatic test equipment. IEEE 1687 is a “descriptive” standard, so there is no provision or limitation on the way the test routines will be executed and if and how they will interact with the System Under Test.

Following IEEE Standard Association (IEEE SA) guidelines, actively used standards should be revised every ten years. IEEE 1149.1 was published in 2013, while IEEE 1687 was published in 2014. Hence, both standards were revisited, and for both, it was determined that a refresh would be beneficial to the community. Consequently, working groups were established and are ongoing. Here, we outline their agenda and progress. Since 2014, other standards that based on 1687 were initiated. In this paper IEEE P1687.1, IEEE P1687.2, and P2654 report on their progress. An in-depth update of IEEE P1687.1 was given during the International Test Conference (ITC) in 2022.

New semiconductor technologies for advanced applications are more prone to defects and imperfections related, among several different causes, to the manufacturing process, aging, and cross-talks. These phenomena negatively affect the circuit’s timing and can be effectively modeled by means of the path delay fault (PDF) model. While path delay testing is currently supported by commercial automatic test pattern generation tools for scan designs, functional testing covering PDFs is not widely adopted, mainly because of the high cost for test generation. On the other side, functional test is already widely adopted for in-field test of stuck-at faults (SAFs), which is often performed resorting to the execution of suitable test programs (Self Test Libraries, or STLs). This approach is attractive, since it can be performed at-speed with limited time constraints and high flexibility, making it a suitable in-field test solutions. Previous work assessed the feasibility and validity of functional approaches based on test programs targeting PDFs. In this work, we present the first systematic method for the development of very high fault coverage test programs for PDFs, which largely outperform test programs written for other fault models. Moreover, the proposed method allows the identification of functionally untestable faults. The effectiveness of the proposed approach was proven on an open-source RISC-V processor core, where 100% coverage of the functionally testable longest paths was achieved, compared with an initial coverage of 0.52% achieved with test programs targeting SAFs. Results demonstrate that shorter paths are also effectively covered.

Modern integrated circuits used in automotive, industrial, consumer, and IoT (Internet of Things) applications often have limited pin counts. Despite this, these devices can be complex, with significant digital and analog content. These features require rigorous testing to address the quality and reliability requirements of these applications. Because of their limited pin count, a TAP controller interface is often not an option or the TAP controller interface itself may not be an option for other reasons, such as die area. Further, the increasing number of IP based designs, along with the increasing availability of IP cores can result in an IP being integrated deep inside a design. Designers, DfT engineers, and test engineers are facing increasing challenges with the integration and testability of IP in their chips. They also have the task of having to test through interfaces that may change depending on the needs of the customers. IEEE P1687.1 is working on processes that will provide a means for automating communications through non-TAP interfaces, making these types of products ideally suited for the techniques currently under consideration for standardization. This paper, reviews the latest topics being discussed by the working group, including the framework for communicating through these interfaces. It discusses how proto buffers (protobufs) can be used to help bridge the gap between a host controller, like an ATE, and an IJTAG network. The approach leverages the concept of Remote Procedural Calls (RPCs) from the IT space and the integer bit vector (intbv) concept from myHDL to support communications through interfaces and between subroutines handling retargeting and handling control of the interface. A model is presented for evaluating the options and various criteria are reviewed with respect to the framework. The paper also explores debug concerns and potential security issues and how those can be addressed.

We demonstrate a Hardware Trojan (HT)-based circuit-to-circuit attack mechanism in the context of Systems-on-Chip (SoCs). The HT trigger is hidden inside the attacking circuit and the HT payload travels from the attacking circuit to the victim circuit via the test infrastructure. The common test infrastructure is configured accordingly by the HT so as to propagate the HT payload. We demonstrate the capability of this HT to perform a denial-of-service attack on an industrial Analog-to-Digital Converter (ADC) connected to a IEEE 1687 test infrastructure.

The industry is moving forward with non-TAP, chip-level interfaces driving IEEE 1687-2014 networks. Recent literature not only describes such interfaces, like I2C and IEEE 1149.7 variants, but also demonstrates that such interfaces to IEEE 1687 are already proven in silicon. Common to those implementations is the need for "private" extensions of IEEE 1687 to make it support non-TAP interfaces. The goal of IEEE P1687.1 is to directly support non-TAP interfaces. In this work, we summarize the thought progression from IEEE 1687's data register callbacks to IEEE P1687.1's transfer function, which allows alignment with IEEE P2654, and possibly IEEE P1687.2.

In recent years, the world of VLSI testing has been living a huge transformation pushed by constraints and requirements coming from a large variety of sources and applications. The traditional need for higher accessibility and controllability led to solutions such as IEEE 1687, while the need for reuse is pushing for innovations like P1687.1. All the while, these same features are raising security concerns for malicious attacks or reverse engineering. Standards usual approach of relying on Domain-Specific Languages to convey information to the EDA tools has difficulty in handling such disparate and often conflicting needs, with the risk of dangerous proliferation of custom and incompatible solutions. In this paper, we show how the usage of Callbacks, defined in P1687.1, can help solve this issue.

This paper introduces a standards-based framework which enables two types of test re-use: direct re-use of test patterns written for low-level components of a system, and access by high-level tests of test features embedded within the low-level components. The underlying mechanism for both is the encapsulation, retargeting, and transformation of test procedures through successive layers of hardware interfaces, as codified in two standards being developed by IEEE Working Groups (P1687.1 and P2654). Examples demonstrate the steps in the process and illustrate both the challenges and opportunities of this approach.

The complexity of modern Systems-on-Chips is steadily increasing, which poses hard challenges for testing. In order to be able to face those challenges, several standards have been proposed through history, such as the latest IEEE 1687 on Reconfigurable Scan Networks (RSNs), which allows dynamic configuration of the test infrastructure for an easier access to embedded instruments and data. This ease of access, however, may constitute a serious threat from the point of view of security, as it may be used by an attacker as an entry point to the internal state of the circuit, especially if the test infrastructure is reused for life-time testing. Some approaches exist to protect the access, but their performances and security levels are limited by the legacy view of test as a static process. In this paper, we propose an innovative solution that exploits the dynamic nature of the IEEE 1687 standard to obtain an Authentication-based Secure Access framework able to provide a trusted and personalized interface to the test infrastructure depending on user-defined security levels.

The disruptive potential of the IEEE 1687 standard does not come from a single innovation, but rather from its capacity of providing a unified framework where heterogeneous approaches can co-exist and interact. In this Special Session, we will present the complementary research activities performed in the TIMA laboratory covering different aspects of the standard (Mixed-Signal instrument testing, Embedded Aging Monitors and Test Access Securization), and their coordination thanks to the Manager-for SoC Test (MAST) software environment.

Path Delay fault test currently exploits DfT-based techniques, mainly relying on scan chains, widely supported by commercial tools. However, functional testing may be a desirable choice in this context because it allows to catch faults at-speed with no hardware overhead and it can be used both for end-of-manufacturing tests and for in-field test. The purpose of this article is to compare the results that can be achieved with both approaches. This work is based on an open-source RISC-V-based processor core as benchmark device. Gathered results show that there is no correlation between stuck-at and path delay fault coverage, and provide guidelines for developing more effective functional test.

Many modern devices have a very limited number of digital pins, yet they are often quite complicated internally. These ICs can't afford the luxury of a traditional JTAG TAP controller and the associated 4 or 5 extra pins. Nonetheless, these devices often contain significant digital and analog content. This complexity makes testing very challenging. Moreover, IP-based design often results in having an instrument buried deep inside a device, the access of which requires transitioning through multiple interfaces and controllers. This is exactly the situation DfT and test engineers face when designing and implementing tests for embedded IP. Techniques proposed for IEEE P1687.1 enable an automated mechanism for retargeting tests through a variety of non-TAP interfaces. This makes these products ideal candidates for IJTAG and IJTAG.1 test strategies. In this paper, we focus on demonstrating how on-chip test functions and IP can be successfully controlled and observed through non-TAP interfaces by controlling data flow using RVF (Relocatable Vector Format) and callbacks. This unique and novel approach ensures tool interoperability and allows tools to model interfaces in the same way, without requiring special descriptions for each one. The paper proposes an automated tool flow for retargeting the tests and provides example implementations on several specialized designs including I2C, an In-System TAP, IEEE 1149.7like interface, and a security block.

Automation has been responsible for the most important breakthroughs in testing, and it is now a fundamental element of the electronics world. Unfortunately, its progress is now limited by several legacy solutions that are implicitly, and sometimes unknowingly, accepted. The duality generation/application of patterns is at the very heart of today's testing ecosystem, but it is being challenged by the very evolutions it, fostered. The IEEE 1687 standard is symptomatic to this: it proposes hardware and software solutions to boost hierarchical and instrument-based testing, but is full application brings the current automated test flow close to breaking point. It is a typical scaling issue: everything seems fine for small-scale systems in the short term, but problems arises when looking at the long-term. In this article, we focus on the long-term vision to uncover and explain these limiting elements. We then propose a new flow that overcomes them, unleashes the full potential of new approaches, and fosters evolution.

The IEEE 1687 standard introduces several novelties, most notably Reconfigurable Scan Networks (RSNs), i.e., scan chains whose length can change dynamically. These architectures offer important advantages but can result in extremely complex integrity test following traditional structural approaches. In this paper, we will present an innovative approach to RSN test and debug based on the functional features of the standard, which is able to greatly speed up test generation time while guaranteeing a precise fault coverage.

Functional Safety standards like ISO 26262 require a detailed analysis of the dependability of components subjected to perturbations. Radiation testing or even much more abstract RTL fault injection campaigns are costly and complex to set up especially for SoCs and Cyber Physical Systems (CPSs) comprising intertwined hardware and software. Moreover, some approaches are only applicable at the very end of the development cycle, making potential iterations difficult when market pressure and cost reduction are paramount. In this tutorial, we present a summary of classical state-of-the-art approaches, then alternative approaches for the dependability analysis that can give an early yet accurate estimation of the safety or security characteristics of HW-SW systems. Designers can rely on these tools to identify issues in their design to be addressed by protection mechanisms, ensuring that system dependability constraints are met with limited risk when subjected later to usual fault injections and to e.g., radiation testing or laser attacks for certification.

When designing an approximate computing system, the selection of the resources to modify is key. It is important that the error introduced in the system remains reasonable, but the size of the design exploration space can make this extremely difficult. In this paper, we propose to exploit a new metric for this selection: data lifetime. The concept comes from the field of reliability, where it can guide selective hardening: the more often a resource handles “live” data, the more critical it becomes, the more important it will be to protect it. In this paper, we propose to use this same metric in a new way: identify the less critical resources as approximation targets in order to minimize the impact on the global system behavior and therefore decrease the impact of approximation while increasing gains on other criteria.

A fundamental part of the new IEEE Std 1687 is the Instrument Connectivity Language (ICL), which allows for abstract description of the scan network. The big novelty if compared to legacy solutions like BSDL is the possibility of describing new topology-enabling elements such as the Scan-Muxes in a behavioural way which can be easily and efficiently exploited by Test Generation Tools to retarget instrument-level operations to top-level patterns. This means that for a given design, the Developer will have to write both the RTL and the ICL descriptions: to the author's best knowledge there is no automated tool to make the translation RTL to ICL. This methodology is error-prone due to the human factor, the difference in intent in the two descriptions and the syntactic and semantic complexity of the languages. Incoherence between ICL and RTL will result in retargeting errors, so it is fundamental to validate the equivalence between the two descriptions. This paper presents an automated methodology that starting from the ICL description is able to generate a set of RTL testbenches that can be simulated against the original RTL model to detect discrepancies and incoherence, and provides quantitative metrics in terms of code and functional coverage. Experimental results are reported on the set of ITC2016 set of benchmark networks.

Current mixed-signal BIST approaches are aimed to move test instrumentation on-chip to reduce the cost of test. However, this can result in a high overhead even for non-time critical DSP tasks that could be executed remotely if a suitable access was available. The new IEEE 1687-2014 standard provides such a portable and efficient infrastructure and can allow decoupling of digital and analog development extremely early in the design flow. In this paper, we demonstrate the approach by applying it to a ΣΔ modulator BIST. In this case study, we exploit 1687 to offload the computationally-heavy spectral analysis that may be responsible of nearly 80% of the total BIST overhead.

Reliability evaluation is a critical task in computing systems. From one side, the results must be accurate enough not to under-or over-estimate the overall system reliability (thus either resulting in a non-reliable system, or a system for which too expensive solutions have been adopted). On the other side, the time required for the analysis should be kept at the minimum. This paper presents some new advances in the reliability assessment of computing systems, by showing techniques targeting both hardware and software levels, and the combination of both.

The new IEEE 1687 standard provides important novelties, such as dynamic topology and access to deeply embedded instruments. Unfortunately, traditional tool flows are not able to fully address this potential. In this paper we will point out the shortcomings of legacy approaches while proposing a new, backward compatible flow optimized for functional usage of instruments.

Evaluating the robustness of circuits with respect to soft errors has become of utmost importance in many application areas. This evaluation must in most cases be refined taking into account the application characteristics in order to avoid too pessimistic results. The main approach used today at design time is based on fault injection campaigns. Emulation can be used to speed up the evaluations, but requires noticeable effort to implement the circuit prototype. This paper presents an approach based on an automated analysis of register lifetime, requiring only one functional simulation of the target application. The approach has been demonstrated on significant circuits. The results show that the proposed approach can be more efficient than emulation in terms of experimental time, without requiring any specific hardware and achieving a good accuracy. The global intrinsic robustness is evaluated and the most critical registers or execution cycles can also be identified with good confidence.

The IEEE 1687 standard enabled the possibility of “alternate access methods” beyond the 1149.1 Test Access Port but did not define how these protocols could be integrated into the 1687 network. In this paper, we propose a solution that is able to support access to the 1687 capabilities through any generic interface.

Named after Prof. E.J. McCluskey, a key contributor to the field of test technology, the 2015 TTTC's Doctoral Thesis Award serves the purpose to i) promote the most impactful doctoral student work, ii) provide the students with the exposure to the community and the prospective employers, and iii) support interaction between academia and industry in the field of test technology. TTTC's E.J. McCluskey Best Doctoral Thesis Award will be given to the winning student of the doctoral student contest and his or her advisor. The award consists of a certificate, an honorarium and an invitation to submit a paper on the presented work to the IEEE Design & Test magazine. In this session, each contestant is given 9 minutes for presentation. After the end of all presentations, a poster session follows, Q&A from a panel of industry experts and the audience. The panel of experts will judge the presented doctoral theses with regards to theoretical advancement, industrial relevance and presentation. The grades submitted by the industrial panel will be combined with the grades given by the academic jury, consisting of distinguished professors. The winner will be announced during the VTS 2015 social event.

The probability of application failures due to soft errors in microprocessors is directly related to the lifetime of data stored in the internal registers. For high performance processors, the accurate analysis of this lifetime is difficult due to the various micro-architecture features, including pipeline registers and fast-forwarding connections managing data dependencies. Using fault injections to evaluate the robustness of a given application program is very time-consuming, even when emulation is used. In consequence, the comparison of several program implementations is often not affordable. We propose a new approach for the evaluation of lifetimes in all the registers of a pipelined processor, ensuring accurate results while reducing drastically the time required for evaluation, thus enabling more software optimizations. In addition, the most critical registers can be quickly identified.

Named after Prof. E.J. McCluskey, a key contributor to the field of test technology, the 2014 TTTC's Doctoral Thesis Award serves the purpose to i) promote the most impactful doctoral student work, ii) provide the students with the exposure to the community and the prospective employers, and iii) support interaction between academia and industry in the field of test technology. TTTC's E.J. McCluskey Best Doctoral Thesis Award will be given to the winning student of the doctoral student contest and his or her advisor. The award consists of a certificate, an honorarium and an invitation to submit a paper on the presented work to the IEEE Design & Test magazine. In this session, each contestant is given 10 minutes for presentation. After the end of all presentations, a poster session follows, Q&A from a panel of industry experts and the audience. The panel of experts will judge the presented doctoral theses with regards to theoretical advancement, industrial relevance and presentation. The grades submitted by the industrial panel will be combined with the grades given by the academic jury, consisting of distinguished professors. The winner will be announced during the VTS 2014 social event.

Named after Prof. E.J. McCluskey, a key contributor to the field of test technology, the 2013 TTTC's Doctoral Thesis Award serves the purpose to promote most impactful doctoral student work, to provide the students with the exposure to the community and the prospective employers, and to support interaction between academia and industry in the field of test technology. TTTC's E.J. McCluskey Best Doctoral Thesis Award will be given to the winning student of the doctoral student contest and his or her advisor. The award consists of a certificate, an honorarium and an invitation to submit a paper on the presented work to the IEEE Design & Test magazine.

Named after Prof. E.J. McCluskey, a key contributor to the field of test technology, the 2013 TTTC's Doctoral Thesis Award serves the purpose to promote most impactful doctoral student work, to provide the students with the exposure to the community and the prospective employers, and to support interaction between academia and industry in the field of test technology. TTTC's E.J. McCluskey Best Doctoral Thesis Award will be given to the winning student of the doctoral student contest and his or her advisor. The award consists of a certificate, an honorarium and an invitation to submit a paper on the presented work to the IEEE Design & Test magazine.

This paper presents a proposal to express JTAG as an asynchronous packet-based protocol while maintaining full backward compatibility. This allows JTAG to transparently access remote units over high-bandwidth functional connections, a feature of special interest, for instance, in the environment of wireless telecommunication infrastructure and interfaces like CPRI or IP.

This paper presents the Open-Circuit Deadlock (OCD), a primitive that allows flexible and scalable securization of a JTAG target, from the cell to the system level.

This paper presents the test instruction set architecture (TISA), an invention that can enable scalable interactive testing to leverage the experience of embedded computing. This approach is applied to an 1149.1 system, obtaining a processor able to efficiently handle instrument-based operations.

Starting from an analysis of the accomplishments and shortcomings of the existing approaches, this paper proposes a new description language able to satisfy all the requirements of IJTAG while providing a fresh and sound base for future evolutions.

Technological evolution is making fault tolerance more and more important in all application fields and it is therefore mandatory to have good strategies to measure its impact on existing systems. A lot of work has been done on fault characterization and modelling, but confusion still abounds when coming to performance loss evaluation. This is especially true for microprocessors, where "performance" is a tricky word to define, cause of a lot of debates and controversies. This article proposes a new and easy-to-apply framework to evaluate performance costs implied by fault tolerance in systems made of both hardware and software. Results are presented on a system based on a Sparc v8 processor and the eCoS operating system.