Recent neuromorphic applications now use spiking neural networks (SNNs) because of their improved computational power compared to previous generations of neural networks. Efficient simulation is essential when using this type of neuron since many events have to be handled on a large number of neurons within the network. In this demonstration, a hardware simulator for SNNs that has applications in image recognition is presented. This SNN uses synchrony processing for efficient event-driven simulation (SPEEDS) which allows parallel computations of synchronized events. SPEEDS differs from common event-driven approaches that serialize every event and can improve significantly the computational efficiency of a SNN simulator. The hardware SNN is implemented on a Xilinx Virtex-6 XC6VLX240T field-programmable gate array (FPGA) and can contain 131 072 neurons. It can process approximately 70 million spikes per second on a 4-bank architecture clocked at 100 MHz. The presentation explains how such a system can be used for image processing tasks like image segmentation, feature extraction and pattern matching to realize a recognition system that can detect several objects in a given image.

Current digital hardware implementations of spiking neural networks usually focus on a time-driven architecture to process the large number of events that occur during a typical simulation. While this type of implementation is practical for simulating biologically accurate neurons, most systems using a simpler neuron model can benefit from an event-driven architecture. In such cases, significant performance improvements are theoretically possible. In practice, however, such implementations do not maximize the available computational power because finding the next event often involves serializing computations. In this paper, a hardware architecture that offers the efficiency of an event-driven algorithm while allowing parallel computations is developed. The architecture uses multiple pipelined processing elements to compute spikes in parallel and a novel comparator tree structure to find the next event in a large network efficiently. The resulting system can implement up to 131 072 neurons on a single FPGA (Xilinx Virtex-6 XC6VLX240T) and processes approximately 70 million spikes per second when using a 4-bank architecture clocked at 100 MHz.

A field programmable gate array (FPGA) implementation of a hardware spiking neural network is presented. The system is able to realize different signal processing tasks using the synchronization of oscillatory leaky integrate and fire neurons. The use of a bit slice architecture and short, local interconnections make it adaptable to projects of various scales. The system is also designed to efficiently process groups of synchronized neurons. A fully connected network of 648 neurons and 419904 synapses is implemented on a stand-alone Xilinx XC5VSX50T FPGA, processing up to 6M spikes/s. We describe the resource usage for the whole system as well as for each functional block, and illustrate the functioning of the circuit on a simple image recognition task.

Abstract — In most logic synthesis systems, technology mapping to a target technology is performed using structural matching techniques. Recently there has been a lot of interest on the usage of boolean techniques to do matching of combinational logic. In this paper, we present an extension of boolean matching to perform technology mapping of sequential elements. The new technique is capable of recognizing the presence of complex sequential elements including JK flip-flops, multiplexed flip-flops, flip-flops with asynchronous behavior and complex latches. The underlying algorithm uses a notion of “timed ” variables and relies on a fast boolean matching technique to achieve efficiency. We have implemented these ideas in a simple technology mapper and contrast the results with two other sequential mapping techniques. I.

The paper presents key technology and physical issues associated with a boundary scan synthesis system. The system accommodates multiple vendor technologies and the requirements of (sometimes non-1149.1 compliant) user specified boundary scan architectures that access core test structures.>

Algorithms and a computer-aided design tool, called Ceres, for technology mapping of both completely specified and incompletely specified logic networks are introduced. The algorithms are based on Boolean techniques for matching, i.e., for the recognition of the equivalence between a portion of a network and library cells. A novel matching algorithm, using ordered binary decision diagrams, is described. It exploits the notion of symmetry to achieve higher computational efficiency. A matching technique that takes advantage of don't-care conditions by means of a compatibility graph is also described. A strategy for timing-driven technology mapping, based on iterative improvement, is presented. Experimental results indicate that these techniques generate good-quality solutions and require short run times and limited memory space.>

A novel algorithm for generating complex CMOS gates from Boolean factored forms is presented. It uses a hierarchical composition of cells corresponding to the subexpressions of a Boolean factored form. Composition rules that allow for constructing the gates in linear time are derived. Cell width/height tradeoffs are made possible to ease pitch-matching. The algorithm has been coded in a pair of programs, called Castor and Pollux. The programs have been used to generate moderately complex layouts, consisting of circuits having up to a few thousand transistors. They can also be used to automatically generate a library of logic gates.>