EDBT 2026 Demo / reviewers in the wild / expert
T. G. Matheson
dblp:00/62
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Integrated circuit design · 13% |
Topics — the 1 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › module generation
cell library generation |
0.0 | 1 | 1997 | Developing a Concurrent Methodology for Standard-Cell Library Generation · DAC 1997 |
Methods — techniques the papers use, named apart from their topics
concurrent engineering · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1997 | Developing a Concurrent Methodology for Standard-Cell Library GenerationabstractThis paper describes the development of a concurrentmethodology for standard cell library generation. Use of anovel physical design automation method enables a high degreeof concurrency among process, circuit, and layout development.In addition to reducing overall time-to-market, the newmethod allows optimization to occur simultaneously across thecircuit, layout, and process design spaces. The result is librarieswith improved density, circuit performance, and process yield. Donald G. Baltus, Thomas Varga, Robert C. Armstrong, John Duh, T. G. Matheson |
DAC | 5 |