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Balkrishna Ramkumar

dblp:00/6635 · DBLP profile ↗
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17ranked-venue papers
8as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 17 · 8 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
7 papers
Parallel and multicore computing · 50% Electronic design automation · 49% High-performance computing · 1%

Topics — the 19 heaviest of 20, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel computing › parallel programming languages
parallel logic programming
0.021994
Machine Independent AND and OR Parallel Execution of Logic Programs: Part II-Compiled Execution · IEEE Trans. Parallel Distributed Syst. 1994
Machine Independent AND and OR Parallel Execution of Logic Programs: Part I-The Binding Environment · IEEE Trans. Parallel Distributed Syst. 1994
Electronic design automation
hardware verification and test
0.011997
ProperTEST: a portable parallel test generator for sequential circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Parallel and multicore computing
parallel algorithms
0.011997
An evaluation of parallel simulated annealing strategies with application to standard cell placement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Parallel and multicore computing › parallel algorithms › parallel combinatorial optimization
parallel simulated annealing
0.011997
An evaluation of parallel simulated annealing strategies with application to standard cell placement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation
physical design
0.011997
An evaluation of parallel simulated annealing strategies with application to standard cell placement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation › physical design
placement
0.011997
An evaluation of parallel simulated annealing strategies with application to standard cell placement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation › hardware verification and test › test generation
sequential circuit test generation
0.011997
ProperTEST: a portable parallel test generator for sequential circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation › physical design › placement › cell placement
standard cell placement
0.011997
An evaluation of parallel simulated annealing strategies with application to standard cell placement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation › hardware verification and test
test generation
0.011997
ProperTEST: a portable parallel test generator for sequential circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Parallel and multicore computing
parallel programming models
0.031994
A Chare Kernel Implementation of a Parallel Prolog Compiler · PPoPP 1990
Machine Independent AND and OR Parallel Execution of Logic Programs: Part II-Compiled Execution · IEEE Trans. Parallel Distributed Syst. 1994
Machine Independent AND and OR Parallel Execution of Logic Programs: Part I-The Binding Environment · IEEE Trans. Parallel Distributed Syst. 1994
Parallel and multicore computing › parallel programming models › task parallelism
and-or parallelism
0.011994
Machine Independent AND and OR Parallel Execution of Logic Programs: Part I-The Binding Environment · IEEE Trans. Parallel Distributed Syst. 1994
Electronic design automation
logic synthesis
0.011994
A portable parallel algorithm for logic synthesis using transduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Parallel and multicore computing
parallel programming environment
0.011994
ProperCAD: A portable object-oriented parallel environment for VLSI CAD · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Parallel and multicore computing
parallel programming models and runtimes
0.011994
A portable parallel algorithm for logic synthesis using transduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › design automation tools
VLSI CAD
0.011994
ProperCAD: A portable object-oriented parallel environment for VLSI CAD · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Parallel and multicore computing › parallel programming models › portable programming models
machine independent parallel programming
0.021994
Machine Independent AND and OR Parallel Execution of Logic Programs: Part II-Compiled Execution · IEEE Trans. Parallel Distributed Syst. 1994
Machine Independent AND and OR Parallel Execution of Logic Programs: Part I-The Binding Environment · IEEE Trans. Parallel Distributed Syst. 1994
Electronic design automation › logic synthesis
combinational logic synthesis
0.011994
A portable parallel algorithm for logic synthesis using transduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
High-performance computing
performance optimization at scale
0.011994
Machine Independent AND and OR Parallel Execution of Logic Programs: Part II-Compiled Execution · IEEE Trans. Parallel Distributed Syst. 1994
Parallel and multicore computing
parallel programming runtimes
0.011990
A Chare Kernel Implementation of a Parallel Prolog Compiler · PPoPP 1990

Methods — techniques the papers use, named apart from their topics

speculative computation · 0.0simulated annealing · 0.0parallel test generation · 0.0multiple markov chains · 0.0MIMD parallelism · 0.0runtime system portability · 0.0parallel-sequential interface · 0.0object-oriented design · 0.0asynchronous message-driven dataflow · 0.0CHARM · 0.0
YearPublicationVenuePosition
1997 ELMO: extending (sequential) languages with migratable objects-compiler support
abstract
Efficient task migration is an important feature in parallel and distributed programs, in particular to support checkpointing and recovery for fault tolerance. It is also very useful in distributed environments like networks of workstations where external loads are often unpredictable and dynamic in nature. We propose simple language extensions (ELMO) to existing sequential programming languages like C, Fortran or C++, that provide an object based task parallel execution model. Tasks may be dynamically created, are location transparent, and may be migrated or check pointed transparently by the system. ELMO's language features, together with the requisite compiler support is presented.
R. J. Richards, Balkrishna Ramkumar, Sukumar G. Rathnam
HiPC2
1997 Perspectives on high performance network computing
Volker Strumpen, Balkrishna Ramkumar, Thomas L. Casavant, Sudhakar M. Reddy
Future Gener. Comput. Syst.2
1997 An evaluation of parallel simulated annealing strategies with application to standard cell placement
abstract
Simulated annealing, a methodology for solving combinatorial optimization problems, is a very computationally expensive algorithm and, as such, numerous researchers have undertaken efforts to parallelize it. In this paper, we investigate three of these parallel simulated annealing strategies when applied to standard cell placement, specifically the TimberWolfSC placement tool. We have examined a parallel moves strategy, as well as two new approaches to parallel cell placement-multiple Markov chains and speculative computation. These algorithms have been implemented in ProperPLACE, our parallel cell placement application, as part of the ProperCAD II project. We have constructed ProperPLACE so that it is portable across a wide range of parallel architectures. Our parallel moves algorithm uses novel approaches to dynamic message sizing, message prioritization, and error control. We show that parallel moves and multiple Markov chains are effective approaches to parallel simulated annealing when applied to TimberWolfSC, yet speculative computation is wholly inadequate.
John A. Chandy, Sung-Ho Kim 0006, Balkrishna Ramkumar, Steven Parkes, Prithviraj Banerjee
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1997 ProperTEST: a portable parallel test generator for sequential circuits
abstract
Parallel algorithms developed for CAD problems today suffer from two important drawbacks. First, they are machine specific, and tend to perform poorly on architectures other than the one for they were designed. Second, the quality of results degrades significantly during parallel execution. In this paper, we address these two problems for an important CAD application: test generation for sequential circuits, We have developed a new parallel test generator, ProperTEST, that is portable across a range of MIMD parallel architectures. This work is part of the ProperCAD project which aims to develop CAD algorithms that run unchanged on shared and nonshared memory machines. We present performance data for ProperTEST on ISCAS 89 sequential circuits on a Sequent Symmetry, an Intel i860 hypercube, an NCUBE/2 hypercube, a network of Sun workstations, and an Encore Multimax. Parallel processing can also be used to improve on the fault coverage possible on one processor in a given amount of time. This was not possible in earlier approaches due to search anomalies. Using ProperTEST, we provide results on ISCAS 89 benchmark programs demonstrating the improvements in fault coverage as the number of processors is increased.
Balkrishna Ramkumar, Prithviraj Banerjee
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1995 Compiling Portable Message-Driven Programs
Balkrishna Ramkumar, C. P. Forbes, Laxmikant V. Kalé
ICPP (2)1
1995 Blocking Entry Points in Message-Driven Parallel Systems
R. J. Richards, Balkrishna Ramkumar
ICPP (2)2
1994 Efficient Task Migration for Message Driven Parallel Execution on Nonshared Memory Architectures
abstract
We discuss the design and implementation of task migration in the Charm parallel programming environment. Charm [7] is a language and run-time system for developing portable parallel applications for MIMD machines that supports a coarse-grained dataflow model of programming. We analyze the performance of migration in detail and demonstrate its efficiency on one nonshared memory machine: the nCUBE/2 hypercube.
Nick Douglas, Balkrishna Ramkumar
ICPP (2)2
1994 A portable parallel algorithm for logic synthesis using transduction
abstract
Combinational logic synthesis is a very important phase of VLSI system design. But the logic synthesis process requires large computing times if near optimal quality of the logic network is desired. Parallel processing is fast becoming an attractive solution to reduce the computational time. Recently, researchers have started to investigate parallel algorithms for problems in logic synthesis and verification. Much of the work in parallel algorithms for CAD reported to date, however, suffers from a major limitation. The parallel algorithms proposed for the CAD applications are designed with a specific underlying parallel architecture in mind. Moreover, incompatibilities in programming environments also make it difficult to port these programs across different parallel machines. As a result, a parallel algorithm needs to be developed afresh for every target parallel architecture. The ongoing project of ProperCAD offers an attractive solution to that problem. It allows the development and implementation of a parallel algorithm on the CHARM runtime system such that it can be executed in all the parallel machines without any change in the program. In this paper, we describe a portable parallel algorithm for logic synthesis based on the Transduction method, called ProperSYN. This algorithm uses an asynchronous message driven data-flow model of computation, with no explicit synchronizing barriers separating different phases of parallel computation as used in many previously developed parallel algorithms. Our algorithm is therefore more scalable to large numbers of processors. The algorithm has been implemented and it runs on a variety of parallel machines. We present results on several benchmark circuits for shared memory MIMD machines like Sequent Symmetry and Encore Multimax, distributed memory MIMD machine like the Intel/860 hypercube and distributed processing systems like networks of SUN workstations.>
Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1994 ProperCAD: A portable object-oriented parallel environment for VLSI CAD
abstract
Most parallel algorithms for VLSI CAD proposed to date work efficiently only on machines that they were designed for. As a result, these algorithms are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. In an effort to address this problem, we are developing a Portable object-oriented parallel environment for CAD algorithms (ProperCAD). The objectives of this research are two-fold: 1) To develop new parallel algorithms that run in a portable object-oriented environment. We accomplish this in two stages. First, we develop CAD algorithms using a general purpose platform for portable parallel programming called CHARM developed at the University of Illinois. Concurrently, we are developing a C++ environment that is truly object-oriented and specialized for CAD applications; and 2) To design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface. This will permit the parallel algorithm to benefit from future developments in sequential algorithms. This approach is described using one CAD application that has been implemented as part of this project-ProperEXT: a flat extractor for VLSI circuits. The algorithm, its implementation, and performance of ProperEXT on a range of parallel machines is presented. The implementation is portable across a variety of parallel platforms without change. It currently runs on an Encore Multimax, a Sequent Symmetry, Inter iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube and a network of Sun Sparc workstations.>
Balkrishna Ramkumar, Prithviraj Banerjee
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1994 Machine Independent AND and OR Parallel Execution of Logic Programs: Part I-The Binding Environment
abstract
We describe a binding environment for the AND and OR parallel execution of logic programs that is suitable for both shared and nonshared memory multiprocessors. The binding environment was designed with a view of rendering a compiler using this binding environment machine independent. The binding environment is similar to closed environments proposed by J. Conery. However, unlike Conery's scheme, it supports OR and independent AND parallelism on both types of machines. The term representation, the algorithms for unification and the join algorithms for parallel AND branches are presented in this paper. We also detail the differences between our scheme and Conery's scheme. A compiler based on this binding environment has been implemented on a platform for machine independent parallel programming called the Chare Kernel.>
Balkrishna Ramkumar, Laxmikant V. Kalé
IEEE Trans. Parallel Distributed Syst.1
1994 Machine Independent AND and OR Parallel Execution of Logic Programs: Part II-Compiled Execution
abstract
For pt.I. see ibid., p. 170-80. In pt.I, we presented a binding environment for the AND and OR parallel execution of logic programs. This environment was instrumental in rendering a compiler for the AND and OR parallel execution of logic programs machine independent. In this paper, we describe a compiler based on the Reduce-OR process model (ROPM) for the parallel execution of Prolog programs, and provide performance of the compiler on five parallel machines: the Encore Multimax, the Sequent Symmetry, the NCUBE 2, the Intel i860 hypercube and a network of Sun workstations. The compiler is part of a machine independent parallel Prolog development system built on top of a run time environment for parallel programming called the Chare kernel, and runs unchanged on these multiprocessors. In keeping with the objectives behind the ROPM, the compiler supports both on and independent AND parallelism in Prolog programs and is suitable for execution on both shared and nonshared memory machines. We discuss the performance of the Prolog compiler in some detail and describe how grain size can be used to deliver performance that is within 10% of the underlying sequential Prolog compiler on one processor, and scale linearly with increasing number of processors on problems exhibiting sufficient parallelism. The loose coupling between parallel and sequential components makes it possible to use the best available sequential compiler as the sequential component of our compiler.>
Balkrishna Ramkumar, Laxmikant V. Kalé
IEEE Trans. Parallel Distributed Syst.1
1992 ProperSYN: a portable parallel algorithm for logic synthesis
abstract
An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asynchronous message driven computing model with no synchronizing barriers, and hence it is scalable to a larger number of processors. Also, the algorithm is portable across a wide variety parallel machines. Experimental results on various parallel machines are presented. The algorithm is built around a well-defined sequential algorithm interface such that there can be benefits from future expansion of the sequential algorithm.>
Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee
ICCAD2
1992 Portable parallel test generation for sequential circuits
abstract
A parallel test generation algorithm, ProperTEST, for sequential circuits that is portable across a range of MIMD parallel architectures is discussed. It uses prioritized execution to ensure consistent speedups as the number of processors is increased. This consistency is achieved without loss of fault coverage with increase in the number of processors. This also permits the use of parallel processing to improve the fault coverage when the execution time is bounded. Results on ISCAS 89 benchmark programs are provided on a shared memory machine, a message passing machine, and a network of workstations. ProperTEST was run unchanged on these different architectures.>
Balkrishna Ramkumar, Prithviraj Banerjee
ICCAD1
1992 ProperCAd: A Portable Object-Oriented Parallel Environment for VLSI CAD
abstract
A portable object-oriented parallel environment for CAD algorithms (ProperCAD) is described. The objectives of this research are twofold: to develop parallel algorithms that are portable and to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface, permitting the parallel algorithm to benefit from future developments in sequential algorithms. The first is achieved by writing the algorithms using the ProperCAD environment, a library of functions that permits portability of parallel CAD algorithms across MIMD machines. Programs written using this environment run unchanged on all parallel machines for which this environment is available.>
Balkrishna Ramkumar, Prithviraj Banerjee
ICCD1
1992 Compile Time Parallel Resource Allocation for Unbounded Tree Structure Task Graphs
Jeff Baxter, Balkrishna Ramkumar, Janak H. Patel
ICPP (1)2
1991 Supporting Machine Independent Programming on Diverse Parallel Architectures
Wayne Fenton, Balkrishna Ramkumar, Vikram A. Saletore, Amitabh Sinha, Laxmikant V. Kalé
ICPP (2)2
1990 A Chare Kernel Implementation of a Parallel Prolog Compiler
abstract
We have designed and implemented a compiler for the parallel execution of Prolog programs as a machine independent application on top of a run time environment for parallel programming called the Chare Kernel. The compiler is based on the Reduce-OR process model for the AND and OR parallel execution of Prolog programs and hence exploits both OR and independent AND parallelism found in Prolog programs. We describe the salient features of the parallel Prolog compiler from the viewpoint of its implementation as a Chare Kernel application. The responsibilities of process creation, load balancing, queueing strategies for work pool management, memory management and interprocess communication are all assumed by the Chare Kernel thereby eliminating these concerns at the application level. We discuss the effectiveness of this separation for a large application like the parallel Prolog compiler. The machine independence property makes the compiler easy to port on all machines, both shared and nonshared, that support the Chare Kernel. The compiler has been implemented on a variety of machines, including the Encore Multimax, the Sequent Symmetry, the Intel iPSC/2 hypercube and the Alliant FX/8. We briefly discuss its performance on a range of benchmarks exhibiting AND, OR and AND/OR parallelism on two of these machines. The speedups obtained are linear, demonstrating the effectiveness of the Chare Kernel as a simple, elegant, yet powerful environment for parallel programming.
Balkrishna Ramkumar, Laxmikant V. Kalé
PPoPP1