Article Free Access Share on Embedded tutorial: essential issues for IP reuse Authors: Daniel D. Gajski University of California, Irvine University of California, IrvineView Profile , Allen C.-H. Wu Tsing Hua University, Taiwan, ROC Tsing Hua University, Taiwan, ROCView Profile , Viraphol Chaiyakul Y Explorations Inc. Y Explorations Inc.View Profile , Shojiro Mori Toshiba Corp., Japan Toshiba Corp., JapanView Profile , Tom Nukiyama NEC Corp., Japan NEC Corp., JapanView Profile , Pierre Bricaud Mentor Graphics Corp. Mentor Graphics Corp.View Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 37–42https://doi.org/10.1145/368434.368504Published:28 January 2000Publication History 19citation399DownloadsMetricsTotal Citations19Total Downloads399Last 12 Months37Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

An algorithm independent layout compaction method for full chip layouts is proposed.The partitioning compaction method cuts up a large layout, compacts each block independently and then merges them to give the final compacted layout.A 16-bit CPU core (28.8Ktransistors) layout was compacted on a standard workstation using this method.Both the computer memory usage and processing time were reduced.Parallel processing is pcssible to further speed up the computation.

This paper describes a new datapath generator that generates high-density mask layouts equivalent to hand-crafted ones.