Embedded memory blocks have been integrated infield-programmable gate-arrays (FPGAs) for over a decade. Their count, as well as their capacity and the number of configurations, has increased over time. This growth poses unique challenges to binding the large number of embedded memory blocks to the data vectors that exist in the applications mapped onto FPGAs. In this paper we discuss how this challenge can be addressed algorithmically.

In this work, a new hardware-based parallel implementation of the iterative conjugate gradient (CG) algorithm for solving such systems of equations is proposed. Fixed point computations are employed to optimize hardware resource usage and to increase parallelism. The proposed implementation adaptively adjusts to variations in the dynamic range of data operands in order to enhance computation accuracy and avoid divergence due to overflow and quantization errors.