In frequency-modulated continuous-wave (FMCW) light detection and ranging (LiDAR) systems, frequency modulation (FM) linearity and continuous-wave (CW) demodulation are the key factors determining overall performance. While most prior works focused on CPU-based linearization and decoding, this study presents a real-time FMCW architecture optimized for autonomous systems. While the system utilizes a generally robust distributed feedback (DFB) laser-based transmitter, it can be susceptible to temperature-induced frequency drift in dynamic autonomous environments. To address these fluctuations, an existing kernel-based nonlinearity tracking method was adopted and further extended into a coarse-to-fine framework for wide-range operation. The main design focus lies in the receiver, which includes a custom analog front-end (AFE) optimized for analog-to-digital converter (ADC) interfacing and multiply-accumulate (MAC) operations, along with a hardware-description-language (HDL)-based real-time decoding process. Experimental results in free space achieved a 0.15% error rate and 0.48-mm STD at 2 m, demonstrating the feasibility of the proposed architecture. In addition, an intensity measurement was conducted to verify the AFE performance.

This brief introduces an in-memory computing (IMC) architecture utilizing a novel analog pop-count circuit based on the one-capacitor-one-nanoelectromechanical (NEM) memory switch device (1C-1N) structure, which performs XNOR and pop-count operations for binary neural networks (BNNs). The NEM memory switch device is a non-volatile memory (NVM) device capable of performing logic-in-memory operations such as XNOR operation. The analog pop-count circuit functions as a readout circuit for the NEM memory switch, reusing the 1C-1N structure as a capacitor digital-to-analog converter. The proposed 1C-1N device and the analog pop-count circuit are simulated using 28-nm CMOS technology. The results show that the 1C-1N device consumes an extremely low read power of 1-fJ/bit and the overall scheme utilizing the analog pop-count circuit, achieves 448.8 TOPS/W while achieving 49.5-% less area than using an analog-to-digital converter (ADC).

While multi-view video system offers users various three-dimensional scenes, its hardware architecture requires more power consumption, chip size and processing time. Each view in Group of Group of Pictures (GoGoP) has different frame structure and different number of reference frames. The multi-view video coding (MVC) performance heavily relies on the frame scheduling architecture for motion estimation (ME) and disparity estimation (DE). Therefore, we need to develop efficient frame scheduling schemes for MVC. In this paper, we propose two frame scheduling schemes: hardware resource aware scheduling (HRaS) and buffering time aware scheduling (BTaS). In the proposed scheduling schemes, the GoGoP is represented by a graph in which edges represent relationship between reference frames and current frames. HRaS relocates frames in GoGoP so that total hardware resources for MVC prediction are reduced. BTaS relocates the frames based on the number of edges so that prediction time and buffering time of the frames are reduced. Through experimental results, we verified the efficiency of the proposed scheduling architectures in terms of power dissipation, area, MVC prediction time, and buffering time.