A novel full-hardware multiply-accumulate (MAC) unit capable of dynamic precision scaling (DPS) and specifically designed for embedded applications is introduced. The MAC autonomously detects and mitigates on-chip overflow and over-representation and eliminates the need for any external software controller. A compact run-time monitoring unit (RMU), within each MAC, dynamically monitors the transitions of carry-out and sign bit, and adjusts the operand representation at the bit level so that any rounding error remains bounded by$2^{-(N_{\text {in}}-1)}$. Bit-sliced input partitioning enables run-time reconfigurability of operand width and accumulation depth without altering the logic topology. Prototyped on a Xilinx Artix-7 FPGA, the proposed unit achieves up to 14% lower dynamic power and 15% higher maximum clock frequency than a conventional fixed-width MAC with the same precision; in a Skywater CMOS 130 nm, it occupies$3.9 \times 10^{3}~\mu \text {m}^{2}$, reaches a critical-path delay of 2.68 ns, and consumes$6.07~\mu $W/MHz.

Nowadays, Human Activity Recognition (HAR) is growing in interest considering the widespread adoption of cheap and healthcare-based devices like Inertial Measurement Units (IMUs) or smartwatches. This study introduces three key advancements in HAR in the context of sports performance monitoring: (i) the development of a stretchable-sensor-based dataset comprising five individuals performing walking, jogging, and running; (ii) the design of an ultra-lightweight image encoding technique for sensor signals; and (iii) the creation of a custom tiny Convolutional Neural Network (CNN) optimized for future near-sensor hardware deployment. The CNN was trained and tested on a literature dataset (w-HAR) and a custom dataset (ST-HAR), both based on a single stretchable sensor. ST-HAR was specifically developed to address the lack of sports-related data from this type of sensor and includes activities performed at speeds from 0.5 to $14 \mathrm{~km} / \mathrm{h}$. Future work will expand this dataset and deploy a custom hardware accelerator for the proposed CNN model.

This paper presents an innovative real-time self-calibration unit designed to enhance the accuracy of pressure sensors following thermal stress. In this way, its use has been enabled in the contest of personal assistance, in particular for the precise localization of people in case of emergencies or in situations where mobility is impaired. The proposed unit comprises a trigger module, which detects uncalibrations, and an error estimator module, which is activated by the trigger and estimates the error to be applied to pressure values through a compact reconfigurable neural network. The system offers reconfigurability, enabling adaptation to various scenarios, such as post-soldering and prolonged exposure to temperatures beyond the nominal range. Validation of the unit was conducted on LPS22HH pressure sensors at STMicroelectronics laboratories. Results demonstrate its capability to recover up to 1.6 hPa and effectively restore accuracy within a nominal range of 0.5 hPa. The system was implemented using STMicroelectronics BCD8 technology, featuring a core area of 0.55 mm2and dynamic power consumption of 4.46 n W in the best scenario. These findings underscore the potential for integrating the system near the sensor, thus realizing an enhanced smart pressure sensor, particularly suited for demanding applications in Industry 4.0, where accurate sensors are indispensable.

The design of a novel, Dynamically Adaptive Accumulator (DAA) is presented. It exploits a new approach to reconfigure the fixed-point input data and multiply-accumulation results to find the optimal trade-off between accuracy and bit-width of data during calculations. The dynamic allocation of resources makes the DAA capable to extend the maximum number of accumulations before an approximation error occurs. The careful design of the DAA results in a very compact architecture and low power implementation that makes the proposed solution very suitable for the acceleration of Neural Network calculations.To validate the effectiveness of our approach, the proposed architecture have been implemented on the Xilinx Artix-7 FPGA and compared it with most-used fixed-point (fixp) and floating-point (fp) alternatives. The results show that the DAA effectively overcomes the counterparts in terms of maximum number of accumulations, area occupation, and power dissipation, presenting a reduction of 84(82)% in LUTs, 77(93)% in FFs and a 7.5× (17×) improvement in Pdyncompared to fixp(fp). The results suggest that the DAA is a promising solution for ISC ANN contexts, offering an improved resource efficiency that make it well-suited for emerging IoT and sensor applications.

The accuracy and computational complexity of keyword spotting (KWS) systems are heavily influenced by the choice of audio features in speech signals. This paper introduces a novel approach for audio feature extraction in KWS by leveraging a convolutional autoencoder, which has not been explored in the existing literature. Strengths of the proposed approach are in the ability to automate the extraction of the audio features, keep its computational complexity low, and allow accuracy values of the overall KWS systems comparable with the state of the art. To evaluate the effectiveness of our proposal, we compared it with the widely-used Mel Frequency Cepstrum (MFC) method in terms of classification metrics in noisy conditions and the number of required operators, using the public Google speech command dataset. Results demonstrate that the proposed audio feature extractor achieves an average classification accuracy on 12 classes ranging from 81.84% to 90.36% when the signal-tonoise ratio spans from 0 to 40 dB, outperforming the MFC up to 5.2%. Furthermore, the required number of operations is one order of magnitude lower than that of the MFC, resulting in a reduction in computational complexity and processing time, which makes it well-suited for integration with KWS systems in resource-constrained edge devices

MEMS pressure sensors are widely used in several application fields, such as industrial, medical, automotive, etc, where they are required to be increasingly accurate and reliable. However, these sensors are very sensitive to mechanical and temperature variations. For example, the soldering process, which involves significant thermal stress, causes drift in the sensor accuracy. This article introduces a digital circuit implementing a very tiny neural network able to compensate for the drift measurement in real time. The circuit is capable of correcting for drift accuracy up to 1.6 hPa, restoring the accuracy to$\pm 0.5\ \text{hPa}$. Synthesis results on TSMC 130 nm CMOS technology show an area occupation of 0.0373$\text{mm}^{2}$and a dynamic power of 1.07$\mu \mathrm{W}$, which enable its easy integration in the digital circuit which is available into MEMS sensor package for pressure measures conditioning.

A novel digital controller for the space-vector pulsewidth modulation (SVPWM) algorithm used in three-phase power inverters is shown. From an analysis of the vector representation of the three-phase triad, the dwell-times evaluation is optimized reducing the needed resource of the hardware. Our proposal is based on the use of only one-sixth of the vectorial plane and on a precalculation of the dwell-times in terms of the maximum modulation index and the minimum carrier frequency. Once obtained the normalized dwell-times, an optimized hardware architecture is proposed to evaluate the effective dwell-times by changing in real time the wanted values of the carrier frequency and of the amplitude. Our architecture excludes the use of external reference signals or processors. We experimentally implement it both on a low-cost field programmable gate array Artix-VII and on a more performing Cyclone-V. Finally, classical and advanced SVPWM techniques are proposed to show the flexibility of our architecture.

A new hardware design of digital system focused to Space Vector Pulse Width Modulation technique is shown. The system performs the real-time control of the output voltage amplitude and of the switching frequency as well as the delay between the three phase output voltages in order to change the direction of rotation of an asynchronous motor. Although the design can be applied to digital control devices, we focused to Field Programmable Gate Array and both architecture and experimental results are shown. The idea is to pre-calculate the dwell-times, which are normalized to the maximum amplitude modulation index, and to relate them at the corresponding switching configurations of the inverter. They are stored in the internal Look-Up Tables and all the operations are performed without any external devices or any external reference signals. A three-phase power inverter prototype supplies a 380VAC- 50Hz - 750W asynchronous motor with on-board Altera Cyclone V FPGA. Our architecture demands 243 FFs and 324 LUTs, which are the 0.66% and 1.75% of the overall system, respectively, avoids internal DSPs and has a low dynamic power dissipation of 0.54mW at a system clock frequency of 100MHz. Our proposal interests those applications where the FPGA manages the overall power system and limited resources are required.

Human Activity Recognition requires very high accuracy to be effectively employed into practical applications, ranging from elderly care to microsurgical devices. The highest accuracies are achieved by Deep Learning models, but these are not easily deployable in handheld or wearable devices with very constrained resources. We therefore present a new HAR system suitable for a compact FPGA implementation. A new Binarized Neural Network (BNN) architecture achieves the classification based on data from a single tri-axial accelerometer. From our experiments, the effect of gravity and the unknown orientation of the sensor cause a degradation of the accuracy. In order to compensate for these issues, we propose a HW-friendly algorithm to pre-process the raw acceleration signal. Moreover, the very low power and hardware friendly BNN has been trained and validated on the PAMAP2 dataset, for which the pre-processing operations increase the accuracy from 51% to 99% in the best case. Aiming for a low-power design, we designed both a custom circuit to perform the pre-processing operations and a hardware accelerator for the BNN. The design on FPGA features a power dissipation of 72 mW and occupies 6788 LUTs.

In this paper, for the first time the design of a HW module to eliminate the effect of the gravity acceleration from data acquired from inertial sensors is presented. A new “hardware friendly” algorithm has been derived from the Rodrigues' rotation formula, which can be implemented in a more compact iterative structure. By exploiting 32-bit floating-point arithmetic, the design is able to combine high accuracy and low power requirements needed by any intelligent Human Activity Recognition system, based on artificial neural networks. Synthesis with 65 nm CMOS std _cells returns a power dissipation below 2 μ W and an area of about 0.05 mm2, Results are the current state-of-the-art for this kind of system and they are very promising for the future integration in smart sensors for wearable applications.

Gabor filters gained a great importance in multimedia processing and visual search applications, thanks to the good spatial frequency and position selectivity, despite of their heavy computational complexity. Further, the large number of parameters to be imposed sets a number of trade-offs between accuracy and complexity making the use of Gabor filters very challenging. In this work, a number of criteria are exploited for a careful choice of the parameters, in order to allow implementing accurate two-dimensional filters, with a computational complexity that can be adapted to target platforms with different capabilities. In order to show this, three hardware designs of a Gabor filter-based edge detection system are derived, implementing two and four orientations, all capable of real-time processing with different Area-Delay-Power performances and accuracies. The derived designs have been implemented on a FPGA-based ASIC prototyping system and synthesized in 90nm CMOS std_cells, returning a maximum operating frequency of 179 MHz and 350 MHz, respectively. Therefore, the proposed filters achieve state-of-the-art performances with the best throughput of 86 and 168 Full-HD (1920×1080 pixels) frames-per-second, for FPGA and std_cell implementations, respectively.

A new 2D convolution-based filter is presented, which is specifically designed to improve visual search applications. It exploits a new radix-3 partitioning method of integer numbers, derived from the weight partition theory, which allows substituting multipliers with simplified floating point (FP) adders, working on 32-b FP filter coefficients. The memory organization allows elaborating the incoming data in raster scan order, as those directly provided by an acquisition source, without frame buffers and additional aligning circuitry. Compared with the existent literature, built around conventional arithmetic circuitry, the proposed design achieves state-of-the-art performances in the reduction of the mapped physical resources and elaboration velocity, achieving a critical path delay of about 4.5 ns both with a Xilinx Virtex-7 field-programmable gate array and CMOS 90-nm std_cells.

In this paper, an architecture design of a hardware accelerator capable to expand the dynamic range of low dynamic range images to the 32-bit high dynamic range counterpart is presented. The processor implements on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to elaborate a full-HD (1920$ \times $1080 pixels) image in 16.6 ms (60 frames/s) on field-programmable logic (FPL), by processing the incoming pixels in streaming order, without frame buffers. In this way, the design avoids the use of external DRAM and can be tightly coupled with acquiring devices, thus to enable the implementation of smart sensors. The processor complexity can be configured with different area/speed ratios to meet the requirements of different target platforms from FPLs to ASICs, obtaining, in both implementations, state-of-the-art performances.