In this paper, we develop a new capacity-approaching code, namely, parallel-concatenated (PC)-Low Density Parity Check (LDPC) convolutional code that is based on the parallel concatenation of trellis-based quasi-cyclic LDPC (TQC-LDPC) convolutional codes. The proposed PC-LDPC convolutional code can be derived from any QC-LDPC block code by introducing the trellis-based convolutional dependency to the code. The capacity-approaching PC-LDPC convolutional codes are encoded through parallel concatenated trellis-based QC recursive systematic convolutional (RSC) encoder (namely, QC-RSC encoder) that is also proposed in this paper. The proposed PC-LDPC convolutional code and the associated encoder retain a fine input granularity on the order of the lifting factor of the underlying block code. We also describe the corresponding trellis-based QC maximum a posteriori probability (namely, QC-MAP) decoder that efficiently decodes the PC-LDPC convolutional code. Performance and hardware implementation results show that the PC-LDPC convolutional codes with the QC-MAP decoder have two times lower complexity for a given bit-error-rate (BER), signal-to-noise ratio, and data rate, than conventional QC-LDPC block codes and LDPC convolutional codes. Moreover, the PC-LDPC convolutional code with the QC-MAP decoder outperforms the conventional QC-LDPC block codes by more than 0.5 dB for a given BER, complexity, and data rate and approaches Shannon capacity limit with a gap smaller than 1.25 dB. This low decoding complexity and the fine granularity make it feasible to efficiently implement the proposed capacity-approaching PC-LDPC convolutional code and the associated trellis-based QC-MAP decoder in next generation ultra-high data rate mobile systems.

Data security has always been a major concern and a huge challenge for governments and individuals throughout the world since early times. Recent advances in technology, such as the introduction of cloud computing, make it even a bigger challenge to keep data secure. In parallel, high throughput mobile devices such as smartphones and tablets are designed to support these new technologies. The high throughput requires power-efficient designs to maintain the battery-life. In this paper, we propose a novel Joint Security and Advanced Low Density Parity Check (LDPC) Coding (JSALC) method. The JSALC is composed of two parts: the Joint Security and Advanced LDPC-based Encryption (JSALE) and the dual-step Secure LDPC code for Channel Coding (SLCC). The JSALE is obtained by interlacing Advanced Encryption System (AES)-like rounds and Quasi-Cyclic (QC)-LDPC rows into a single primitive. Both the JSALE code and the SLCC code share the same base quasi-cyclic parity check matrix (PCM) which retains the power efficiency compared to conventional systems. We show that the overall JSALC Frame-Error-Rate (FER) performance outperforms other cryptcoding methods by over 1.5 dB while maintaining the AES-128 security level. Moreover, the JSALC enables error resilience and has higher diffusion than AES-128.

In this paper, we propose a new type of code called Trellis-based Quasi-Cyclic (TQC)-LDPC convolutional code, which is a special case of protograph-based LDPC convolutional codes. The proposed TQC-LDPC convolutional code can be derived from any QC-LDPC block code by introducing trellis-based convolutional dependency to the code. The main advantage of the proposed TQC-LDPC convolutional code is that it allows reduced decoder complexity and input granularity (which is defined as the minimum number of input information bits the code requires to generate a codeword) while maintaining the same bit error-rate as the underlying QC-LDPC block code ensemble. We also propose two related power-efficient encoding methods to increase the code rate of the derived TQC-LDPC convolutional code. The newly derived short constraint length TQC-LDPC convolutional codes enable low complexity trellis-based decoders and one such decoder is proposed and described in this paper (namely, QC-Viterbi). The TQC-LDPC convolutional codes and the QC-Viterbi decoder are compared to conventional LDPC codes and Belief Propagation (BP) iterative decoders with respect to bit-error-rate (BER), signal-to-noise ratio (SNR), and decoder complexity. We show both numerically and through hardware implementation results that the proposed QC-Viterbi decoder outperforms the BP iterative decoders by at least 1 dB for same complexity and BER. Alternatively, the proposed QC-Viterbi decoder has 3 times lower complexity than the BP iterative decoder for the same SNR and BER. This low decoding complexity, low BER, and fine granularity makes it feasible for the proposed TQC-LDPC convolutional codes and associated trellis-based decoders to be efficiently implemented in high data rate, next generation mobile systems.

The interest in short range communication has significantly increased in the last decade with the introduction of different wireless connectivity standards and their evolution such as IEEE802.11n/ac and IEEE802.11ad. New demands for higher resolution multimedia applications such as UHD push for higher data rates to exceed 30Gbps. This high data rate demand requires short range standards to adopt a new approach to accommodate these rates. Millimeter wave enable high bandwidth usage which implies higher capacity to accommodate 10–100Gbps data rates. However, the high data rate pose big challenges to both the system algorithm and architecture. In this paper, we propose a novel FPGA-based high-throughput beamforming MIMO system for millimeter wave short range communication. We present our first realization of a complete millimeter wave short range communication system, which includes RF frontend, ADC/DAC, beamforming control, synchronization, channel estimation, MIMO precoding/detection, and channel encoder/decoder. The design works at millimeter carrier frequency with 500MHz bandwidth and 2-channel MIMO Beamforming. We show realtime application test results as captured in the millimeter wave system.

In this paper we propose a new dual quantization-domain LDPC decoder, which requires only 3-bit messages between the check nodes and the variable nodes. To reduce complexity and save power, check nodes processing is entirely in the 3-bit domain. However, to avoid loss in performance, the variable nodes processing is in a higher bit precision domain. A non-linear mapping is used to map the messages from one quantization domain to the other. Simulations and hardware evaluation of the proposed decoder showed greater than 50% reduction in power consumption with only 0.1 dB (0.2 dB) loss in bit-error-performance when compared to a reference 5-bits scaled Min-Sum decoder over the AWGN (fading) channel.

Wireless LAN systems have been continuously evolving to provide ~10X increase in data rates every five years, exploiting higher mmWave frequencies and larger bandwidths, such as IEEE 802.11ad, providing 6.76 Gb/s using 2.16 GHz of bandwidth at 60 GHz. One of the key technical challenges to successful commercialization of these large bandwidth systems is power consumption. In this paper, we focus on reducing the idle listening mode power consumption where the device is actively looking for packets and the power consumption is dominated by the high speed ADCs. We propose a low power and bandwidth-scalable synchronization design for large bandwidth systems by developing reduced bandwidth modes in high-speed ADCs used in such systems. We study the impact of the proposed synchronization design on the detection probability, false alarm, AGC design and symbol timing estimation. Comparisons of our design using a bandwidth reduction of 4 with the existing IEEE 802. Had synchronization design show no loss in AWGN and a 0.8 dB loss in fading for an equivalent acquisition time and false alarm rate while providing a 33% power reduction in idle mode, assuming the ADCs consume 50% of the total idle power consumption. We also provide backward compatibility with current IEEE 802.11ad systems with limited impact on performance and power consumption.

In this paper, we present a novel FPGA-based high-throughput beamforming MIMO receiver for millimeter wave mobile communication. With vast spectrum and small antenna element size, millimeter wave communication becomes very attractive and promising to support next generation mobile communication (5G). However, the high data rate requirement challenges both algorithm and architecture. In order to support the high data rate and to reduce the overhead of selecting the best beam pair, we propose a novel beamforming synchronization scheme more suitable for mobile communication. By further optimizing the algorithm and the architecture, we present a complete mobile receiver based on FPGA, which includes RF frontend, ADC, beamforming control, synchronization, channel estimator, soft MAP detector, and channel decoder. The design operates at 28 GHz carrier frequency with 500 MHz bandwidth. The throughput can reach 1.52 Gbps. We also performed the indoor and outdoor over-the-air transmission field tests. This work provides a platform for future millimeter wave mobile communication research.

Visible Light Communication (VLC) is a short range wireless transmission of visible light through free space. The light source can be based on Light-Emitting Diodes (LEDs), that are becoming common use in our future connected home where they can be simultaneously used for both illumination (i.e. LED TVs, Light bulbs, etc.) and communication with appropriate photodiodes in the receiver side. VLC can be adapted to mobile devices enabling new types of short range applications such as HD video streaming. However, many of the new emerging mobile applications require increasingly high data rates; some can even exceed 1 Gbps. In this paper, we propose new optical/electrical front-end and baseband systems that achieve the required bit rate of 1 Gbps over free space. We also detail the implementation challenges of the low power VLC communication system for a mobile device. Specifically we focus on the new VLC baseband system and propose new baseband scheme with state-of-the-art LDPC channel coder. Finally, we will present the results of the new proposed gigabit baseband system as well as lab test results of a single channel VLC front-end running at 540 Mbps and 1080 Mbps.

In this paper, we present a method for creating LDPC codes which are specifically designed to be hardware friendly. Our method involves constraining the cyclic shift values in the base H-matrix to reduce the complexity of the cyclic shift hardware. We show that the decoder hardware implementation for these codes has higher throughput and lower power consumption than decoders designed for traditional LDPC codes. We provide results showing that these codes maintain the error rate performance expected of LDPC codes while achieving these throughput and power consumption improvements.

LDPC codes are becoming popular in next generation high throughput wireless standards since they can provide a level of parallelism with sufficient performance to support the high gigabit rate. In this paper, we propose a new method for LDPC decoding called Parallel Processing Layered (PPL). The new method aims to optimize the latency and power efficiency of LDPC decoding to enable significant increase of the processing rate, thereby saving battery power for mobile devices. We provide performance results in different channel models using the newly defined WiGig standards, and compare them to the conventional decoding methods. We show that the new proposed LDPC decoding architecture converges 2x faster than conventional (i.e. Flooding) methods.

The quality of any communication system is greatly determined by the performance excellence of the selected channel coding scheme. In this work, we propose algorithms for designing LDPC channel coding schemes. The proposed designs are suitable for achieving Gigabit communications with relatively low-power consumption. We design LDPC code family with fixed block length and no puncturing. Also, starting with an LDPC code base-family, we construct LDPC code families with longer block length but decodable using the same hardware as the base-family. We propose a unified decoder architecture, which can decode all LDPC codes in the designed base-family as well as all LDPC codes in the derived code families with longer block length.