One of the primary clinical observations for screening the novel coronavirus is capturing a chest x-ray image. In most patients, a chest x-ray contains abnormalities, such as consolidation, resulting from COVID-19 viral pneumonia. In this study, research is conducted on efficiently detecting imaging features of this type of pneumonia using deep convolutional neural networks in a large dataset. It is demonstrated that simple models, alongside the majority of pretrained networks in the literature, focus on irrelevant features for decision-making. In this paper, numerous chest x-ray images from several sources are collected, and one of the largest publicly accessible datasets is prepared. Finally, using the transfer learning paradigm, the well-known CheXNet model is utilized to develop COVID-CXNet. This powerful model is capable of detecting the novel coronavirus pneumonia based on relevant and meaningful features with precise localization. COVID-CXNet is a step towards a fully automated and robust COVID-19 detection system.

This paper presents the algorithm and architecture of the decimal floating-point (DFP) logarithmic converter, based on the digit-recurrence algorithm with selection by rounding. The proposed approach can compute faithful DFP logarithm results for any one of the three DFP formats specified in the IEEE 754-2008 standard. In order to optimize the latency for the proposed design, we mainly integrate the following novel features: 1) using the redundant carry-save representation of the data path; 2) reducing the number of iterations by determining the number of initial iteration; and 3) retiming and balancing the delay of the proposed architecture. The proposed architecture is synthesized with STM 90-nm standard cell library and the results show that the critical path delay and the number of clock cycles of the proposed Decimal64 logarithmic converter are 1.55 ns (34.4 FO4) and 19, respectively, and the total hardware complexity is 43,572 NAND2 gates. The delay estimation results of the proposed architecture show that its latency is close to that of the binary radix-16 logarithmic converter, and that it has a significant decrease on latency compared with a recently published high performance CORDIC implementation.

In this paper, we propose a high performance processor for elliptic curve cryptography (ECC) over GF(2163) by using polynomial presentation. It has three finite field (FF) RISC cores and a main controller to achieve instruction-level parallelism (ILP) with pipeline so that the largely parallelized algorithm for elliptic curve point multiplication can be well suited on this platform. Instructions for combined FF operation are proposed to decrease clock cycles in the instruction set. The interconnection among three FF cores and the main controller is obtained by analyzing the data dependency in the parallelized algorithm. The whole design is implemented on Xilinx XC4VLX80 FPGA device, and it can reach 185 MHz with 20,807 slices. The total time required for one ECC point scalar operation is 7.7μs in 1428 cycles.

This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the digit-recurrence algorithm. The converter can calculate accurate logarithms of 32-bit DFP numbers which are defined in the IEEE 754-2008 standard. Redundant digit e1is obtained by look-up table in the first iteration and the rest redundant digits ejare selected by rounding the scaled remainder during the succeeding iterations. The sequential architecture of the proposed 32-bit DFP logarithmic converter is implemented on Xilinx Virtex-II Pro P30 FPGA device and then synthesized with TMSC 0.18-um standard cell library. The implementation results indicate that the maximum frequency of the proposed architecture is 47.7 MHz in FPGA and 107.9 MHz in TMSC 0.18-um technology. The faithful 32-bit DFP logarithm results can be obtained in 18 cycles.

This paper presents a novel design and implementation of a 7-digit fixed-point decimal-to-decimal logarithmic converter. Two approaches, binary-based decimal approximation algorithm (Algorithm 1) and decimal linear approximation algorithm (Algorithm 2), are proposed and investigated. It shows that decimal linear approximation algorithm (Algorithm 2) is error-free in conversion between decimal and binary formats and also able to reduce maximum absolute error from binary-based Algorithm 1’s 0.00399 (integer cases) and 0.0483 (fraction cases) to 0.000994 (both cases). The Algorithm 2 is modeled in VHDL and implemented using combinational logic only in a Xilinx Virtex-II Pro P30 FPGA device. The logarithms results can be obtained in a single clock cycle, running at 50.9 MHz.