Fuel cells are a promising power source for future data centers, offering high energy efficiency, low greenhouse gas emissions, and high reliability. However, due to mechanical limitations related to fuel delivery, fuel cells are slow to adjust to sudden increases in data center power demands, which can result in temporary power shortfalls. To mitigate the impact of power shortfalls, prior work has proposed to either perform power capping by throttling the servers, or to leverage energy storage devices (ESDs) that can temporarily provide enough power to make up for the shortfall while the fuel cells ramp up power generation. Both approaches have disadvantages: power capping conservatively limits server performance and can lead to service level agreement (SLA) violations, while ESD-only solutions must significantly overprovision the energy storage device capacity to tolerate the shortfalls caused by the worst-case (i.e., largest) power surges, which greatly increases the total cost of ownership (TCO). We propose SizeCap, the first ESD sizing framework for fuel cell powered data centers, which coordinates ESD sizing with power capping to enable a cost-effective solution to power shortfalls in data centers. SizeCap sizes the ESD just large enough to cover the majority of power surges, but not the worst-case surges that occur infrequently, to greatly reduce TCO. It then uses the smaller capacity ESD in conjunction with power capping to cover the power shortfalls caused by the worst-case power surges. As part of our new flexible framework, we propose multiple power capping policies with different degrees of awareness of fuel cell and workload behavior, and evaluate their impact on workload performance and ESD size. Using traces from Microsoft's production data center systems, we demonstrate that SizeCap significantly reduces the ESD size (by 85%ofor a workload with infrequent yet large power surges, and by 50% for a workload with frequent power surges) without violating any SLAs.

Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurable fabric to accelerate portions of large-scale software services. Each instantiation of the fabric consists of a 6×8 2-D torus of high-end Stratix V FPGAs embedded into a half-rack of 48 machines. One FPGA is placed into each server, accessible through PCIe, and wired directly to other FPGAs with pairs of 10 Gb SAS cables. In this paper, we describe a medium-scale deployment of this fabric on a bed of 1,632 servers, and measure its efficacy in accelerating the Bing web search engine. We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system when ranking candidate documents. Under high load, the largescale reconfigurable fabric improves the ranking throughput of each server by a factor of 95% for a fixed latency distribution—or, while maintaining equivalent throughput, reduces the tail latency by 29%.

An assessment is a complex, labor-intensive process in which a number of things can go awry. This can cause the assessment team to waste time and may result in the presentation of an inaccurate picture of compliance status. By identifying and responding to risks and issues which can negatively impact upon the efficiency of the assessment process, an organization can maximize the opportunity for assessors to accurately determine an organization's true level of compliance. Accurate, relevant findings provide a solid foundation from which to facilitate continuous improvement and achievement of higher process goals. This paper describes the strategies used to successfully conduct an assessment against the Capability Maturity Model for Software in the Motorola iDEN/spl trade/ Subscriber Group engineering organization in April 2003. The techniques can be applied to other similar appraisal methods (including ISO 9000 audit or a SCAMPI/sup SM/ for CMMI/sup /spl reg//) which involve some combination of interviews and evidence review.

Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ECR tests may be degraded by a large number of normal transitions in a circuit, which may bury the fault impact on the overall current. For deterministic ECRs, the fault-oriented ECR tests are generated with an algorithm to minimize the number of normal transitions not related with the sensitizable path of the target faults. For generalized ECRs, however, the test patterns are generic without targeting any specific faults and therefore may cause a significant amount of transient activities in a CUT. This issue is addressed in this paper by utilizing a DFT technique, multiple scan chain design. This technique virtually partitions the circuit into several sections, so that the transitions in each section can be much less compared with those in the whole circuit. The fault impact can be more significant with fewer transitions in the circuit, which hence increases the ECR test effectiveness. The anti-process-variation property of the ECR metric is also demonstrated through a negligible lotto-lot shift. Finally, the effectiveness of ECR tests with different thresholds is compared with existing traditional tests. 1

Very-Low-Voltage, Ultra-Low-Voltage (a modified version of Minimum-Voltage), and Energy Consumption Ratio (a recently developed test metric) tests are applied as supplemental tests along with existing traditional tests to a biomedical IC product. The effectiveness and efficiency of these supplemental tests are evaluated and compared with some major traditional tests. The effectiveness analysis indicates that Ultra-Low-Voltage and Energy Consumption Ratio tests identified potentially defective devices from good devices. The efficiency analysis shows that the Energy Consumption Ratio test is much more efficient than Very-Low-Voltage, Ultra-Low-Voltage and major traditional tests.

Dynamic I/sub dd/ test techniques are obtaining more attention from both academia and industry, because of their ability to further improve product quality beyond tests based primarily on I/sub ddq/ test and other traditional test techniques. Normal process variations in wafer fabrication decrease the defect coverage and affect the application of dynamic I/sub dd/ test techniques. Energy Consumption Ratio (ECR) test, a recent test metric based on dynamic currents, shows its tolerance to process variations, over other dynamic test techniques. We investigate this technique as a method of providing additional test coverage to production wafers that were fabricated using two different planarization technologies. One set was fabricated with a Spin-on-Glass (SOG) planarization technology, and the other set with Chemical Mechanical Polishing (CMP). The SOG wafers used in our experiments contain defects known as "poisoned vias." We show that the ECR is effective in detecting defects of this type where other traditional test methods are not.