Using physiological signals to control brain-computer interface (BCI) becomes more popular. Among many kinds of physiological signals, Electrooculography (EOG) signal is more stable which can be used to control BCI systems based on eye movement detection and signal processing methods. Also, the use of electroencephalographic (EEG) signals has become the most common approach for a BCI because of their usability and strong reliability. In this paper, we described a signal processing method, which uses a wireless EEG-based BCI system designed to be worn near forehead that can detect both EEG and EOG signals, for detecting eye movements to have 9 direction controls (via EOG) and one action of execution (via EEG). This system included a wireless EEG signal acquisition device, a mechanism that can be worn stably, and an application program (APP) with signal processing algorithms. This algorithm and its classification procedure provided an effective method for identifying eye movements and attention. Finally, we designed a baseball game to test the BCI system. The results demonstrated that player can control the game well with high accuracy.

We design a method to incorporate color information into the framework of CENsus Transform histogram (CENTRIST), a state-of-the-art visual descriptor for scene categorization. The newly proposed color CENTRIST descriptor describes global shape information by not only gradient derived from intensity values but also color variations between pixels in local image patches. Through extensive evaluations on various datasets, we demonstrate that the color CENTRIST descriptor is not only easily to be implemented, but also reliably achieves performance over that of CENTRIST.

Due to power restriction of some laser sources, the use of same optical power in every bit duration (i.e., same bit power) of double-weight codes in optical code-division multiple access (O-CDMA) with differential quality-of-service (QoS) was previously studied and analyzed with approximated performance. In this paper, an exact analytical model is formulated and validated with computer simulation, establishing accurate relationships of code weight, chip power, and bit power with code performance. Besides better understandings the role of power control in variable-weight O-CDMA with differential QoS, such accurate analytical model is important for power-sensitive applications, such as in-service monitoring and fiber-fault surveillance in optical networks and sensor-identification in fiber-sensor systems with the use of optical codes.

To provide differential quality-of-service in optical code-division multiple access, variable-weight codes were proposed and analyzed under a conventional assumption of identical power in every optical pulses (i.e., same chip power). To account for power limit of some laser sources, we assume the use of same optical power in each bit duration (i.e., same bit power) in this paper. For illustration, we focus our study on double-weight codes under both same-chip-power and same-bit-power assumptions. A new and better approximate performance-analytical model for double-weight codes is developed and validated with computer simulation. We show that heavy-weight codes do not always perform better than light-weight codes under the same-bit-power assumption, contrary to previous findings under the same-chip-power assumption.

According to a study from Gartner Group [13], mostly successful attacks exploit software applications and operating systems that were not properly configured or vulnerability patched. Regarding enterprises, there are far reaching consequences if their online services are attacked and compromised. As a result, making their systems safer is becoming a higher priority. In this paper, we proposed a system to resolve the vulnerability and misconfiguration issues. In the vulnerability part, we focus on the aspect of vulnerability assessment. We use CVSS (Common Vulnerability Scoring System) to measure the vulnerability severity to the organization and help administrators with patch management. For the configuration portion, we use CCE (Common Configuration Enumeration) configuration scanner to scan the system and determine the presence of the misconfiguration in the system. The experiments show that our system can help administrators to understand their own systems and enhance system security.

This paper proposes a scalable and high available (HA) architecture for implementing cost effective security switches. In this architecture, each "security switch" consists of a traditional layer-2 switch and a "security switch engine (SSE)" which provides packet content inspection service. These two components are connected via a Gigabit Ethernet link. A mechanism is proposed to interconnect a group of "security switches" to provide the HA feature. A system of four security switches is implemented and the experimental results show that the HA function works successfully even only one SSE is active. The SSE is implemented with full intrusion prevention function on a standard high performance Industrial PC with the performance of 1.2Gbps for UDP packets and 400Mbps for TCP flows. Therefore the proposed security switch architecture can be realized in a very cost effective mechanism to provide Intranet protection.

Cluster-based servers are one of the best solutions to build high-performance, scalable, and reliable Internet Web servers. A number of researches have been done about enabling the dispatcher in cluster-based Web servers to route the users requests based on higher layer information, such as URLs. Hashing functions and tree structure are often used to achieve the goal of URL lookup, but they may cause the problem of collision and result in unacceptable performance. This paper presents a fast scalable URL lookup mechanism that uses content addressable memory (CAM) as the basic hardware components. Our scheme not only supports exact matching of URL lookup, but also provides prefix-matching lookup ability so that it is very practically for URL content-filtering like systems. The proposed scheme takes constant time to lookup a URL and furnishes a rate of 100 million lookups per second. By applying the entry reuse concept, the expensive CAM space can be used in a more efficient way to store more URLs. With this fast URL lookup engine, the performance of content dispatchers or URL content filters can be greatly improved.

This paper proposes a cost effective architecture for network security switch to deep inspect the traffic among switching ports. A security service engine (SSE) with packet deep inspection ability is also designed to accompany with manageable L2 switches. By properly configuring the VLAN parameters, packets from switch ports of the L2 switch are forwarded to the SSE, via the gigabit Ethernet interface, for deeply inspection. For security reason, abnormal/malicious packets are dropped by the SSE directly while normal packets are forwarded back to the switch to the correct output port. To evaluate the performance and latency of the proposed architecture, a cost effective P4-based SSE is also implemented as an intrusion detection and prevention system (IPS) with layer-7 content inspection function. The obtained measurements show that the proposed architecture is practical with high throughput and low latency. With IPC-based SSE implementation, the traditional L2 switches can now provide content security service in a very cost effective way.

Network intrusion detection systems (NIDS) monitor packets on the network and attempts to discover if a hacker is attempting to break into a system. The matching of packet strings against collected signatures dominates signature-based NIDS performance. Network processors are one of the fastest growing segments of the semiconductor market, because they are designed to provide scalable and flexible solutions that can accommodate change quickly and economically. This work presents a fast string matching algorithm (called FNP) over the network processor platform that conducts matching sets of patterns in parallel. FNP needs less number of memory accesses against conventional pattern-matching algorithms. Another contribution of this work is to highlight that, besides total number of searching patterns, shortest pattern length is also a major influence on NIDS multi-pattern matching algorithm performance.

Network intrusion detection systems (NIDSs) are one of the latest developments in security. The matching of packet strings against collected signatures dominates signature-based NIDS performance. Network processors are also one of the fastest growing segments of the semiconductor market, because they are designed to provide scalable and flexible solutions that can accommodate change quickly and economically. This work presents a fast string-matching algorithm (called FNP) over the network processor platform that conducts matching sets of patterns in parallel. This design also supports numerous practical features such as case-sensitive string matching, signature prioritization, and multiple-content signatures. This efficient multiple-pattern matching algorithm utilizes the hardware facilities provided by typical network processors instead of employing the external lookup co-processors. To verify the efficiency and practicability of the proposed algorithm, it was implemented on the Vitesse IQ2000 network processor platform. The searching patterns used in the present experiments are derived from the well-known Snort ruleset cited by most open-source and commercial NIDSs. This work shows that combining our string-matching methodology, hashing engine supported by most network processors, and characteristics of current Snort signatures frequently improves performance and reduces number of memory accesses compared to conventional string-matching algorithms. Another contribution of this work is to highlight that, besides total number of searching patterns, shortest pattern length is also a major influence on NIDS multipattern matching algorithm performance.