Digital video databases in compressed form are becoming widely available. In applications such as video browsing, and picture in picture, for a lower bitrate, there is a need to down-sample the video before transmission. The conventional approach to downscale a compressed video sequence is to decompress it at the video server, perform the down-sampling in the pixel domain and then recompress it for efficient delivery. This process is computationally intensive due to the motion estimation process required during the recompression phase. In the alternative compressed domain approach, the motion vectors of the downscaled video sequence are computed directly from the motion vectors of the original full size stream. In this paper we propose a compressed domain technique that generates a better estimate for the downscaled motion vectors. Simulations suggest that the performance achieved with the proposed method is superior by up to 1 dB to the current compressed domain techniques.

A new multicasting mechanism for RAM-based shared-buffer ATM switches is introduced. Multiple logical output queues, including a new queue for multicast and broadcast cells, are all interleaved into a single physical buffer as in the single-queue switch architecture. Queues are hardware-independent and full buffer-sharing is achieved. Cells are scheduled in the multicast queue based on their priority level and service type as in the unicast queues. A single copy of a multicast cell is kept in the queue. The cell is sent to all of its destinations upon its service time. A unicast cell in a given output queue can still be sent if it has higher priority than a multicast cell. In this case a unicast copy of the multicast cell for that output port is placed in the output queue. This copying scheme requires neither extra hardware nor extra memory space for duplicated cells. A new grouping algorithm is presented which supports the incorporation of the multicast queue and the unicast queues into a single overall queue.

Groups of cells, such as cells belonging to different priority levels, that are all placed in one queue, can be identified by using labels or tags to distinguish them from each other. We describe a buffering device called a sequencer, which can distinguish logical queues within the same physical queue, and at the same time can successfully schedule the service among these logical queues. Scheduling the service among cells, VCs, or groups of cells in ATM switches is necessary to provide guaranteed QoS for each connection which is a major goal of ATM networks. The proposed sequencer is quite flexible and can realize different scheduling algorithms in different levels, including per VC scheduling. The sequencer can operate in real time and at very high speeds. It has a simple and modular architecture and can be implemented in a single chip. The site of the buffer can be increased simply by cascading several sequencers. The sequencer can be used as a traffic shaper, input buffer, output buffer, or a queue controller of RAM-based switches.

In this paper we introduce a new approach to ATM switching. We propose an ATM switch architecture which: uses only a single shift-register-type buffering element to store and queue the cells; and within the same physical queue switches the cells by organizing them in logical queues destined to different output lines. The buffer is also a sequencer which allows flexible ordering the cells in each logical queue to achieve any appropriate scheduling algorithm. This switch is proposed for use as the building block of large-scale multi-stage ATM switches and as the scheduler/controller for the RAM-based switches. The single queue switch implements output queueing and performs full buffer sharing. The hardware complexity is low. The number of input and output lines can vary independently without affecting the switch core. The size of the buffering space can be increased by simply cascading the buffering elements to each other.

We introduce a new approach to ATM switching. We propose an ATM switch architecture which uses only a single shift-register-type buffering element to store and queue cells, and within the same (physical) queue, switches the cells by organizing them in logical queues destined for different output lines. The buffer is also a sequencer which allows flexible ordering of the cells in each logical queue to achieve any appropriate scheduling algorithm. This switch is proposed for use as the building block of large-stale multistage ATM switches because of low hardware complexity and flexibility in providing (per-VC) scheduling among the cells. The switch can also be used as scheduler/controller for RAM-based switches. The single-queue switch implements output queueing and performs full buffer sharing. The hardware complexity is low. The number of input and output lines can vary independently without affecting the switch core. The size of the buffering space can be increased simply by cascading the buffering elements.