A new diode-based approach (called D-2D) for implementing Digital-to-Analog Converter (DAC) is presented. This approach provides a viable option for implementing DACs for ultra-low power applications. By using diodes instead of resistors, resistances in the giga-ohms range are achieved without sacrificing area, resulting in ultra-low current consumption. Since the diodes are operating in subthreshold region with extremely low subthreshold current, the issue of gate oxide tunnelling leakage becomes a significant source of error. A back-to-back diode configuration is proposed to significantly reduce the effect of this leakage current. Device stacking technique is employed to reduce the subthreshold leakage in the unit diode and in the DAC switches. Simulation results in 22nm TSMC process of an 8-bit D-2D DAC achieves $\sigma_{\mathrm{I}\mathrm{N}\mathrm{L}}/\sigma_{\mathrm{D}\mathrm{N}\mathrm{L}}$ better than 0.3LSBs with the DAC core consuming ~220pA of current for a reference of 580mV.

This paper presents a new active-capacitor-assisted dual-loop output-capacitorless low-dropout regulator (OCLDO). As opposed to the conventional PMOS-based OCLDOs where the current load range is limited due to significant output variations under large load step changes, a dual-loop control scheme is proposed to improve the slew rates at transient-critical nodes and the regulation accuracy. To further speed up the loop response, a single-point-detection (SPD) active capacitor located at the output detects both positive and negative output variation together and reduces undershoot/overshoot and settling time without using any passive output capacitor. Implemented in a standard 65nm CMOS process, the proposed OCLDO delivers a maximum load current of 200mA. It only uses a small compensation capacitor of 0.86pF and achieves fast settling time of 110ns. It also has small undershoot / overshoot voltages of ≤ 160mV under load step changes of 200mA/100ns. Compared with previous designs, this work presents a fully on-chip PMOS OCLDO that provides the best transient FOM of 0.62fs.

This paper presents a 3$^{rd}$ order continuous-time sigma-delta modulator (CTSDM) with a hybrid loop filter, which is composed of passive RC integrator and proposed continuous-time delay (CTD) based integrator. The proposed CTD integrator enables a low power design that can operate under low supply voltages with high power efficiency. The modulator was designed in 65nm CMOS technology. Simulation results show that it has 80dB dynamic range and 75dB SNDR over 15MHz signal bandwidth at 2GHz sampling frequency, while dissipating 0.45mW from a 1.0V supply. A power efficiency of 3.25 fJ/conv is achieved.

Owing to its reduction in hardware complexity and power consumption, hybrid beam-forming has become one of the most promising substitutes for fully digital beam-forming (FDB) in large antenna array systems. In conventional hybrid beam-forming (CHB) architecture, phase shifters are designed to operate at RF band and inaccuracies of the RF phase shifts are unavoidable in practice. Furthermore, these RF phase shifters still consume considerable power if implemented as active devices or a large space/area on dice (form factor) if implemented as passive devices. This issue becomes more critical for massive MIMO systems where lower power consumption and smaller form factor are much desired due to the large number of antenna elements. Aiming at reducing power consumption and form factor of the receiver, we investigate a new method to insert phase shifts via adjusting sampling-offset on sample and hold (S&H) circuit. Based on this method, a new receiver architecture with RF under-sampling technique and adjustable S&H circuit is proposed. We also develop a method to find out the required phase shifts for the beam-forming in the proposed receiver architecture. Performance evaluation at 28 GHz band shows that the proposed technology gives practically the same bit error rate (BER) performance as the CHB architecture but yields advantages in terms of power consumption, chip area, and beam-forming phase errors, which makes it appealing for massive MIMO systems.

This paper presents a between-pair skew (BPS) compensator for parallel data communications. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a wide-bandwidth voltage controlled data delay line. A 5-Gb/s sub-bit BPS compensator in 0.13-$\mu{\rm m}$CMOS occupies approximately 0.038-${\rm mm}^{2}$active die area and dissipates 22.5 mW.

This paper presents a ground switching load modulation scheme for passive HF RFID transponders. The proposed modulation scheme allows HF transponders to communicate with the reader in the strong field with a higher modulation index using simple RF clamps, compared with conventional resistive and capacitive load modulation schemes. Also presented is a ground-isolated voltage doubler rectifier to eliminate effects of parasitic diodes in CMOS processes, thereby increasing the communication distance. A 13.56-MHz transponder prototype was implemented in a standard CMOS 0.35-process. Measurement results show that the proposed transponder achieves over 35-mV modulation depth for the magnetic field strength from 0.15 to 7.5 A/m.

This paper studies the problems of optimizing power dissipation for simultaneous buffer insertion/sizing and uniform wire sizing (BISUWS), and simultaneous buffer insertion/sizing and tapered wire sizing (BISTWS). For BISUWS, we analyze the optimal total power dissipation under the delay constraints as well as the power-delay tradeoff. For BISTWS, we study the problems of minimizing power dissipation with optimal delay constraints or with a given delay penalty. We derive optimal solutions for both cases. These solutions can be used to efficiently estimate the power dissipation for long single wires in the interconnect designs.

In this paper, we propose a novel time-domain based method, discrete singular convolution algorithm, for computing steady-state response in nonlinear circuit. Properties and advantages of discrete singular convolution method are discussed, compared with some other approaches. The accuracy and efficiency of this method are tested by the numerical experiments.

This paper describes a power conversion and data recovery system for a microwave powered sensor platform. A patch microwave antenna, a matching filter and a rectifier make the system frontend and implement the RF-to-DC conversion of power carrier. The efficiency of the power conversion is as high as 47% with an input power level 250 µW at 2.45 GHz. Then, a 0.18 µm CMOS integrated circuit extracts the clock and the digital data. A modified pulse amplitude modulation scheme is used to modulate the data on the 2.45 GHz carrier frequency for combined data and power transmission; this scheme allows very low power consumption of the entire IC to be less than 10 µW and making the system suitable for an autonomous wireless connected sensor module.

The paper presents a mixed signal CMOS feedforward neural-network chip with on-chip error-reduction hardware for real-time adaptation. The chip has compact on-chip weighs capable of high-speed parallel learning; the implemented learning algorithm is a genetic random search algorithm: the random weight change (RWC) algorithm. The algorithm does not require a known desired neural network output for error calculation and is suitable for direct feedback control. With hardware experiments, we demonstrate that the RWC chip, as a direct feedback controller, successfully suppresses unstable oscillations modeling combustion engine instability in real time.

Presents a parallel learning neural network chip, which is used to perform real-time output feedback control on a nonlinear dynamic plant. The controlled plant is a simulated unstable combustion process. Neural networks provide an adaptive sub-optimal control that does not need any prior knowledge of the system. In addition, the hardware neural network presented here utilizes parallelism to achieve speed independent of the size of the network enabling real-time control. On-chip learning ability allows the hardware neural network to learn online as the plant is running and the plant parameters are changing. Also described is the experimental setup used to obtain the results.