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Meng-Xiang Lee

dblp:01/2895 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › routing
multilayer routing
0.112008
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › physical design › routing › steiner tree construction
obstacle-avoiding rectilinear steiner minimum tree
0.112008
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation
physical design
0.112008
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › physical design
routing
0.112008
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › physical design › routing
steiner tree
0.112008
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008

Methods — techniques the papers use, named apart from their topics

steiner tree construction · 0.1spanning graph · 0.1
YearPublicationVenuePosition
2008 Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
abstract
Given a set of pins and a set of obstacles on routing layers, a multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges within layers and vias between layers and avoids running through any obstacle to construct a Steiner tree with a minimal total cost. The ML-OARSMT problem is very important for many very large scale integration designs with pins being located in multiple routing layers that contain numerous routing obstacles incurred from IP blocks, power networks, prerouted nets, etc. As a fundamental problem with extensive practical applications to routing and wirelength/congestion/timing estimations in early design stages, it is desired to develop an effective algorithm for the ML-OARSMT problem to facilitate the design flow. However, there is no existing work on this ML-OARSMT problem. In this paper, we first formulate the ML-OARSMT problem with rectangular obstacles and then identify key different properties of this problem from its single-layer counterpart. Based on the multilayer obstacle-avoiding spanning graph, we present the first algorithm to solve the ML-OARSMT problem. Our algorithm can guarantee an optimal solution for any two-pin net and many multiple-pin nets. Experiments show that our algorithm results in 33% smaller total costs on average than a construction-by-correction heuristic which is widely used for Steiner-tree construction in the recent literature.
Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4