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Rafael Santschi

dblp:01/2906 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%
Computer graphics and multimedia
1 paper
Audio and music processing · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
low-power circuit design		 0.112006
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm · DAC 2006
Integrated circuit design
VLSI design		 0.112006
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm · DAC 2006
Audio and music processing › hearing aids
hearing aid signal processing		 0.012006
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm · DAC 2006
Audio and music processing
speech enhancement		 0.012006
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm · DAC 2006

Methods — techniques the papers use, named apart from their topics

resource sharing · 0.1gate-level simulation · 0.1
YearPublicationVenuePosition
2006 Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm
abstract
This paper analyzes the power-area trade-off of functionally equivalent architectural implementations of a speech enhancement algorithm for hearing aids. Gate-level simulations and measurements show that an optimum degree of resource sharing (0.60 mW in a 0.25 /spl mu/m CMOS process) is more energy-efficient than both the fully time-multiplexed (1.42 mW) and the isomorphic architecture (1.54 mW), without overly large area overhead (0.77 mm/sup 2/ against 0.43 mm/sup 2/ and 4.31 mm/sup 2/, respectively).
Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
 DAC6