Reversible image authentication (RIA) schemes are systems based on reversible watermarking designed for image authentication. They can offer several advantages over other approaches, such as integrating the image and its authentication information into a single signal and providing block-wise tamper localization capability. However, existing RIA schemes report a large number of unembeddable blocks, and limited effectiveness in tamper localization and detection accuracy across different attacks. To handle these issues, this work proposes an RIA scheme with high-resolution tamper-localization capabilities and high detection accuracy. A reversible watermarking method is also proposed, which produces more embeddable blocks and less image distortion than existing techniques. Experimental results show that when a protected image is attacked, the tampered blocks are effectively detected and localized. In addition, compared to a state-of-the-art scheme, the proposed scheme is more effective for block-wise tamper detection against splicing, collage, and copy-move attacks, while it is competitive at the pixel level against these attacks.

Advances in quantum computing have posed a future threat to today’s cryptography. With the advent of these quantum computers, security could be compromised. Therefore, the National Institute of Standards and Technology (NIST) has issued a request for proposals to standardize algorithms for post-quantum cryptography (PQC), which is considered difficult to solve for both classical and quantum computers. Among the proposed technologies, the most popular choices are lattice-based (shortest vector problem) and hash-based approaches. Other important categories are public key cryptography (PKE) and digital signatures. Within the realm of digital signatures lies SPHINCS+. However, there are few implementations of this scheme in hardware architectures. In this article, we present a hardware-software architecture for the SPHINCS+ scheme. We utilized a free RISC-V (Reduced Instruction Set Computer) processor synthesized on a Field Programmable Gate Array (FPGA), primarily integrating two accelerator modules for Keccak-1600 and the Haraka hash function. Additionally, modifications were made to the processor to accommodate the execution of these added modules. Our implementation yielded a 15-fold increase in performance with the SHAKE-256 function and nearly 90-fold improvement when using Haraka, compared to the reference software. Moreover, it is more compact compared to related works. This implementation was realized on a Xilinx FPGA Arty S7: Spartan-7.

Pixel value ordering (PVO) is a prominent method for reversible data hiding, which has gained increasing research interest in recent years due to its effective performance producing high-fidelity marked images. PVO-based methods performance lies on block dimensions and thresholds for classification. However, most methods determine proper parameters by performing exhaustive searches in restricted search spaces . In this paper, we present a novel Pixel Value Ordering technique based on Genetic Algorithms (PVO-GA) to address these issues. PVO-GA uses flexible sized blocks to take advantage of different block features, to better exploit image redundancy. A genetic algorithm is introduced to optimize the embedding process since the solutions space is greatly expanded. Results showed that PVO-GA achieves satisfactory levels in terms of the introduced distortion while significantly reduces the computational cost needed to find the optimal set of insertion parameters when compared to previous methods.

Cellular or fine grained Genetic Algorithms (GAs) are a massively parallel algorithmic approach to GAs. Decentralizing their population allows alternative ways to explore and to exploit the solutions landscape. Individuals interact locally through nearby neighbors while the entire population is globally exploring the search space throughout a predefined population's topology. Having a decentralized population requires the definition of other algorithmic configuration parameters; such as shape and number of individuals within the local neighborhood, population's topology shape and dimension, local instead of global selection criteria, among others. In this article, attention is paid to the population's topology dimension in cGAs. Several benchmark problems are assessed for 1, 2, and 3 dimensions while combining a local selection criterion that significantly affect overall selective pressure. On the other hand, currently available high performance processing platforms such as Field Programmable Gate Arrays (FPGAs) and Graphics Processing Units (GPUs) offer massively parallel fabrics. Therefore, having a strong empirical base to understand structural properties in cellular GAs would allow to combine physical properties of these platforms when designing hardware architectures to tackle difficult optimization problems where timing constraints are mandatory.

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Cryptographic algorithms are used to enable security services that are the core of modern communication systems. In particular, Hash functions algorithms are widely used to provide services of data integrity and authentication. These algorithms are based on performing a number of complex operations on the input data, thus it is important to count with novel designs that can be efficiently mapped to hardware architectures. Hash functions perform internal operations in an iterative fashion, which open the possibility of exploring several implementation strategies. In the paper, two different schemes to improve the performance of the hardware implementation of the SHA-2 family of algorithms are proposed. The main focus of the proposed schemes is to reduce the critical path by reordering the operations required at each iteration of the algorithm. Implementation results on an FPGA device show an improvement on the performance on the SHA-256 algorithm when compared against similar previously proposed approaches.

This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detectors require sorting, a linear sorter based on a First In First Out (FIFO) schema is used. The proposed architecture can be used as a specialized module or co-processor for Software Defined Radar (SDR) applications. The results of implementing the architecture on a Field Programmable Gate Array (FPGA) are presented and discussed.

This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the confidentiality and integrity algorithms defined for the Universal Mobile Telecommunication System (UMTS) standard. The first proposal is a pipelined design and the second implements an iterative approach. The throughput for these architectures turn out to be higher than the throughput achieved by other proposals.