In this paper, we propose a new search technique for ATPG, called CONCAT [1], which (a) is based on AND/OR reasoning, (b) integrates conflict driven learning, and (c) avoids over specification of test vectors. The technique works seamlessly (i) between Boolean and non-Boolean gates in industrial designs, (ii) across phases in latch-based designs, (iii) between justification and propagation tasks in sequential ATPG, and (iv) across faults in the fault list. Experimental results on combinational ISCAS circuits against SAT-based ATPG, show that we can reduce the test vector specification by upto 74%, with consistent improvement in performance and capacity. We integrated the CONCAT technique into Intel's existing ATPG tool, called Aztec, and obtained upto 67% speed-up and upto 14% more ATPG effectiveness on industrial designs.

A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of a domino gate in the presence of crosstalk is developed and exploited by a new efJicient timing analysis algorithm. The algorithm uses a single, breadth-jirst traversal to compute delays in the presence of crosstalk. Thus, it avoids the iterative methods commonly employed for static CMOS circuits. The timing analysis technique is used to generate test input vectors that exercise the worst-case delays of a multiplier circuit implemented using domino logic. Hspice simulation results demonstrate that the technique identiJes test vectors that produce circuit delay that satisfy the targeted value in the presence of crosstalk.

As technology scales into the deep submicron regime, capacitive coupling between signal lines becomes a dominant problem. Capacitive coupling is more acute for domino logic circuits since an irreversible, unwanted gate output transition can result. We present a timed test generation methodology for CMOS domino circuits that assigns the circuit inputs so that capacitively-coupled aggressors of a victim line transition in time proximity which creates a noise effect that is propagated within the clock-cycle constraint. Experiments for a multiplier reveal that a high level of accuracy is achieved without significant test generation time, resulting in a nearly 50% reduction in the number of sites earlier believed to be susceptible to crosstalk failure.

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. The authors address the charge-sharing noise issue. Specifically, they develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simulations. The model is used to generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests are validated using Hspice simulations on industrial circuits and it is also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. In this paper, we address the charge sharing noise issue. Specifically, we develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simulations. The model is used to generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests were validated using Hspice simulations on industrial circuits and it was also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.

Capacitative coupling will become a dominant problem due to increased parasitic capacitance between adjacent wires and faster signal switching rates. The coupling problem is more acute for domino logic circuits since an irreversible gate output transition can result. We present a method to analyze domino circuits for susceptibility to crosstalk failures from a layout-extracted netlist. Specifically, sites in the circuit that may fail due to crosstalk are identified. In addition, failure sites are partitioned into two categories (faults or design errors) based on their likelihood of occurrence in the context of manufacturing variations. The method has been implemented and applied to a dual-rail domino Wallace tree circuit with little loss in accuracy, resulting in a 37X speedup over a full analysis using Hspice.

We present an automated procedure for improving the testability of a product by improving the testability of cells in the cell library. This method was applied to a scan flip-flop from Cyrix's standard cell library. Based on this analysis, some design and layout changes were suggested, which brought down the probability of difficult-to-detect faults by 70%, without compromising the performance or increasing the area of the circuit.