Binary addition is one of the most frequent operations in computation systems. Dedicated carry logic in modern FPGA devices allows ripple-carry adders to outperform other kinds of adders. However, a long carry chain is still time-consuming in a wide bit-width adder. We propose a new methodology to partition the long carry chain into short segments and organize these segments by applying carry-select or carry-skip schemes. Therefore, the resulting adder can take advantage of fast carry ripple locally, reduce the long signal delay globally, and produce high performance calculations.

An efficient matrix solver is critical to the analytical placement. As the size of the matrix becomes huge, the multilevel methods turn out to be more efficient and more scalable. Algebraic Multigrid (AMG) is a multilevel technique to speedup the iterative matrix solver [10]. We apply the algebraic multigrid method to solve the linear equations that arise from the analytical placement. A layout based clustering scheme is put forward to generate coarsening levels for the multigrid method. The experimental results show that the algebraic multigrid solver is promising for analytical placement.