EDBT 2026 Demo / reviewers in the wild / expert
Mohammad Dashti 0002
dblp:01/4316-2
· DBLP profile ↗
4ranked-venue papers
2as first author
1since 2021 · last 2021
0009-0004-6267-5617ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Memory systems · 62% Performance modeling and evaluation · 14% Processor architecture and microarchitecture · 12% | |
| Software engineering, system software, and programming languages
2 papers |
Operating systems · 82% Concurrent programming · 18% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
processing-in-memory |
0.5 | 1 | 2021 | A Case Study of Processing-in-Memory in off-the-Shelf Systems · USENIX ATC 2021 |
Operating systems › resource management
memory management |
0.2 | 1 | 2013 | Traffic management: a holistic approach to memory placement on NUMA systems · ASPLOS 2013 |
Memory systems › non-uniform memory access
NUMA data placement |
0.2 | 1 | 2013 | Traffic management: a holistic approach to memory placement on NUMA systems · ASPLOS 2013 |
Performance modeling and evaluation
workload characterization |
0.1 | 1 | 2021 | A Case Study of Processing-in-Memory in off-the-Shelf Systems · USENIX ATC 2021 |
Processor architecture and microarchitecture
chip multiprocessor |
0.1 | 1 | 2011 | A Case for NUMA-aware Contention Management on Multicore Systems · USENIX ATC 2011 |
Parallel and multicore computing › parallel scheduling
NUMA-aware scheduling |
0.1 | 1 | 2011 | A Case for NUMA-aware Contention Management on Multicore Systems · USENIX ATC 2011 |
Concurrent programming › transactional memory
contention management |
0.0 | 1 | 2011 | A Case for NUMA-aware Contention Management on Multicore Systems · USENIX ATC 2011 |
Methods — techniques the papers use, named apart from their topics
trace-driven simulation · 0.3kernel implementation · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | A Case Study of Processing-in-Memory in off-the-Shelf Systems
Joel Nider, Craig Mustard, Andrada Zoltan, John Ramsden, Larry Liu, Jacob Grossbard, Mohammad Dashti 0002, Romaric Jodin, Alexandre Ghiti, Jordi Chauzi, Alexandra Fedorova |
USENIX ATC | 7 |
| 2017 | Analyzing memory management methods on integrated CPU-GPU systemsabstractHeterogeneous systems that integrate a multicore CPU and a GPU on the same die are ubiquitous. On these systems, both the CPU and GPU share the same physical memory as opposed to using separate memory dies. Although integration eliminates the need to copy data between the CPU and the GPU, arranging transparent memory sharing between the two devices can carry large overheads. Memory on CPU/GPU systems is typically managed by a software framework such as OpenCL or CUDA, which includes a runtime library, and communicates with a GPU driver. These frameworks offer a range of memory management methods that vary in ease of use, consistency guarantees and performance. In this study, we analyze some of the common memory management methods of the most widely used software frameworks for heterogeneous systems: CUDA, OpenCL 1.2, OpenCL 2.0, and HSA, on NVIDIA and AMD hardware. We focus on performance/functionality trade-offs, with the goal of exposing their performance impact and simplifying the choice of memory management methods for programmers. Mohammad Dashti 0002, Alexandra Fedorova |
ISMM | 1 |
| 2013 | Traffic management: a holistic approach to memory placement on NUMA systemsabstractNUMA systems are characterized by Non-Uniform Memory Access times, where accessing data in a remote node takes longer than a local access. NUMA hardware has been built since the late 80's, and the operating systems designed for it were optimized for access locality. They co-located memory pages with the threads that accessed them, so as to avoid the cost of remote accesses. Contrary to older systems, modern NUMA hardware has much smaller remote wire delays, and so remote access costs per se are not the main concern for performance, as we discovered in this work. Instead, congestion on memory controllers and interconnects, caused by memory traffic from data-intensive applications, hurts performance a lot more. Because of that, memory placement algorithms must be redesigned to target traffic congestion. This requires an arsenal of techniques that go beyond optimizing locality. In this paper we describe Carrefour, an algorithm that addresses this goal. We implemented Carrefour in Linux and obtained performance improvements of up to 3.6 relative to the default kernel, as well as significant improvements compared to NUMA-aware patchsets available for Linux. Carrefour never hurts performance by more than 4% when memory placement cannot be improved. We present the design of Carrefour, the challenges of implementing it on modern hardware, and draw insights about hardware support that would help optimize system software on future NUMA systems. Mohammad Dashti 0002, Alexandra Fedorova, Justin R. Funston, Fabien Gaud, Renaud Lachaize, Baptiste Lepers, Vivien Quéma, Mark Roth |
ASPLOS | 1 |
| 2011 | A Case for NUMA-aware Contention Management on Multicore Systems
Sergey Blagodurov, Sergey Zhuravlev, Mohammad Dashti 0002, Alexandra Fedorova |
USENIX ATC | 3 |