Compaction is the CAD tool used to pack rough sketches or symbolic diagrams to produce IC layouts. Manual compaction is tedious, time-consuming, and error-prone; automated compaction tools can greatly shorten the layout design cycle. This paper reviews the historical background and the major developments in the field of compaction, emphasizing subjective evaluations rather than objective descriptions. The major approaches covered are constraint-graph, shear-line, and virtual-grid. Various ideas for further reducing chip area (such as inserting jog points, shortening wires, dense packing, 2-D compaction, and interactive tools) are also discussed. Because of the critical role of efficient algorithms in VLSI CAD systems, analyses of computational complexities are also included.