Thermal issues are becoming increasingly critical due to rising power densities in high-performance chip design. The need for fast and precise full-chip thermal analysis is evident. Although machine learning (ML)-based methods have been widely used in thermal simulation, their training time remains a challenge. In this article, we proposed a novel physics-informed separation of variables solver (PISOV) to significantly reduce training time for fast full-chip thermal analysis. Inspired by the recently proposed ThermPINN, we employ a least-square regression method to calculate the unknown coefficients of the cosine series. The proposed PISOV method combines physics-informed neural network (PINN) and separation of variables (SOVs) methods. Due to the matrix-solving method of PISOV, its speed is much faster than that of ThermPINN. On top of PISOV, we parameterize effective convection coefficients and power values for surrogate model-based uncertainty quantification (UQ) analysis by using neural networks, a task that cannot be accomplished by the SOV method. In the parameterized PISOV, we only need to calculate once to obtain all parameterized results of the hyperdimensional partial differential equations. Additionally, we study the impact of sampling methods (such as grid, uniform, Sobol, Latin hypercube sampling (LHS), Halton, and Hammersly) and hybrid sampling methods on the accuracy of PISOV and parameterized PISOV. Numerical results show that PISOV can achieve a speedup of$245\times $, and$10^{4}\times $over ThermPINN, and PINN, respectively. Among different sampling methods, the Hammersley sampling method yields the best accuracy.

Timing-driven routing is crucial in complex circuit design. Existing shallow-light Steiner tree construction methods balance between wire length (WL) and source-sink path length (PL) but lack in delay. Conversely, previous delay-driven methods prioritize delay but result in longer WL and PL, making them suboptimal. In this article, we show that simultaneously reducing the WL and PL can effectively reduce the delay. Furthermore, we investigate how delay changes during the reduction of PL. Guided by the theoretical findings, we develop a rectilinear shallow-light Steiner tree construction algorithm designed to reduce delay meanwhile maintaining a bounded WL. Furthermore, a delay-driven edge shifting algorithm is proposed to fine tune the tree’s topology, further reducing delay. We show that our proposed edge shifting algorithm can return a local Pareto optimal solution when repeatedly applied. Experimental results show that our algorithm achieves the lowest total delay compared to previous methods while maintaining competitive WL. Moreover, for nets with pins that have timing information, our algorithm can generate the most suitable Steiner Tree based on the timing information. In addition, extended experiments highlight the positive impact of constructing rectilinear Steiner trees with minimized total delay. Our codes will be available athttps://github.com/Whx97/Delay-driven-Steiner-Tree.

This article proposes a novel analytical steady-state thermal simulation framework considering anisotropic thermal conductivity for 3-D integrated circuits (3D-ICs) that combine an adaptive rectangular discretization algorithm with a conformal meshing strategy to achieve enhanced computational efficiency and accuracy. To address the challenges of arbitrary power density distributions in modern 3D-ICs, we develop an adaptive rectangle approximation method that dynamically adjusts rectangular partition sizes based on local gradient analysis and error-controlled discretization criteria. The derived rectangular thermal sources are subsequently processed through a conformal meshing technique that preserves geometric fidelity while minimizing mesh complexity. For analytical solution derivation, we employ the domain decomposition method effectively to divide the multilayer 3-D structure into several individual layers with customized general solutions. Interlayer thermal coupling is resolved through interfacial boundary condition enforcement. Numerical simulations demonstrate that the proposed analytical thermal method achieves significant performance improvements, exhibiting$60\times $acceleration over conventional finite element method (FEM) implementations while maintaining a maximum absolute error (MAX) below 0.5 K across multiple benchmark cases with 3D-ICs.

In the thermal design of 3-D integrated circuits (ICs) and packages, numerical simulation is extensively employed to investigate the impact of model parameters on hotspot temperature. However, conventional simulation approaches usually require plenty of computational resource and thus lead to expensive time cost for thermal designs. In this paper, we present a novel technique to efficiently and accurately conduct thermal simulation of 3-D ICs and packages, potentially reducing thermal design timeline from weeks to minutes. The proposed thermal resistance network derivative (TREND) model facilitates to focus the solution domain on the crucial regions for thermal designs and accelerate simulation without sacrificing accuracy. Also, the TREND model protects the internal details of chips and packages, which is quite suitable for modular thermal designs. The flexibility, accuracy, and efficiency of the proposed method are demonstrated through several numerical examples. Compared with the commercial software, a speed-up of 2695x is achieved in a typical thermal design case without the loss of accuracy.

In this work, we propose a fast full-chip thermal numerical analysis approach based on an enhanced physics-informed neural networks (PINN) framework. The new method, called ThermPINN, leverages both PINN-based DNN optimization framework and analytic solutions of simplified thermal problems for solving thermal partial differential equations (PDE). The resulting ThermPINN leads to more efficient training speed of DNN networks and more scalability for solving large PDE problems. Specifically, we propose to partially enforce physics laws based on closely related analytic solutions to simpler problems. As a result, we are able to significantly reduce the number of variables in the loss function and easily meet boundary conditions. To consider the impact of various ambient temperatures and effective convection coefficients, which are influenced by different design parameters and run-time conditions, we develop a parameterized thermal analysis technique. This technique enables design space exploration and uncertainty quantification (UQ), which are critical for ensuring the reliability of integrated circuits under various operating conditions. The numerical results on alpha21264 processor show that the proposed ThermPINN has 2× speedup and 3× better accuracy over the state-of-the-art thermal simulator, VarSim. The experimental results for 2-D full-chip thermal analysis of 3171 cases show that the proposed parameterized ThermPINN considering both training and inference time can achieve a 6× speedup over commercial COMSOL with an average mean absolute error (AE) of 0.47 K. In terms of training time, the proposed parameterized ThermPINN is 11× faster than the parameterized plain PINN with similar accuracy. The UQ analysis with 5000 samples for maximum temperature propagated from ambient temperature shows that the parameterized ThermPINN and parameterized plain PINN are 113× and 22× faster than COMSOL, respectively.

In this paper, we propose a novel machine learning-based approach, called PostPInn- Em, for solving the partial differential equations for stress evolution in a confined metal interconnect multi-segment trees during the post-voiding stage for fast electromigration (EM) check for interconnects. The new approach is based on an enhanced two-stage Physics-Informed Neural Networks (PINN) framework in which the physics law for a single wire is enforced first and then atomic flux conservation and stress continuity at the inter-segment junctions of wire segments are then fulfilled to reduce the number of variables of loss functions for the fast training process. Existing two-stage PINN method uses supervised learning method for modeling a single wire under various atomic flux conditions for the first stage, which turns out to be much more difficult for post-voiding phase due to arbitrary non-zero initial conditions. To mitigate this problem, we propose a new closed-form parameterized formula for stress solution of single wires with variable bound-ary conditions based on the Laplace transformation methods. Furthermore, we derive the analytic solutions for wire segment with and without voiding as not all the wire segments will have voids during the post-voiding phase. Numerical results on some synthesized multi-segment interconnects show that the proposed PostPINN-EM can achieve more than 100X speedup compared to FEM based tool COMSOL with the expense of less than 1% accuracy. Compared to the state of the art tool EMspice v1.0 [1], this method can achieve more than 25X speedup with similar accuracy compared to golden results from COMSOL.

In this work, we propose a novel physics-informed sparse regression (PISR) framework to solve stress evolution (described by Korhonen’s equations) in general multisegment wires using an unsupervised learning scheme. Unlike the existing physics-informed neural network (PINN) framework, the PISR method trains the trainable weights through the Moore–Penrose generalized inverse algorithm used in extreme learning machine (ELM), which is extremely faster than the backpropagation algorithm. To improve the accuracy of PISR for complex multisegment interconnects, we employ domain decomposition schemes in both space and time. For each subdomain, we use different trainable weights but the same shared neural network to represent each subsolution, which leads to more efficient memory usage. Furthermore, we propose to use sparse matrix techniques to accelerate the training speed of the PISR method and prove that the resulting PISR has linear time complexity for analyzing tree-structured interconnects. Finally, we divide the time into many time intervals and apply an autoregressive model to simulate each time interval in sequence to further improve scalability and reduce memory cost so that the PISR method can perform EM analysis for large-scale multisegment interconnects. Experimental results on different kinds of interconnect structures show that the proposed PISR method has the same accuracy level as the numerical methods. The results on$N_{T}$T-junctions interconnect trees show that the proposed PISR method indeed demonstrates true linear time complexity. Furthermore, PISR can deliver$8.9\times $,$20.6\times $, and$1284\times $speedups over the recently proposed semi-analytic method (ASOV), finite difference method accelerated with model order reduction (FDM-MOR), FDM for the interconnect with$N_{T}= 5000$, respectively. Furthermore, we show that PISR also achieves an$818\times $speedup in training over the plain PINN method based on the traditional backpropagation algorithm.

Thermoelectric cooler (TEC) is a promising active cooling device to remove the localized hot spots precisely in VLSI chips. In this article, we use a novel implicit physics-constrained neural networks (called IPCNNs) to build a surrogate model for the single TEC device with the reduction from 3-D to 1-D. First, the surrogate model represented by the deep neural networks (DNNs) allows parameterization of key design and running parameters, such as current density, length, and thermal boundary conditions of the TEC. Second, the proposed method tries to partition the physics laws into two different groups, which then are enforced by supervised learning and physics-informed neural networks (PINNs) framework sequentially. Such implicit PCNN scheme can lead to much faster training speed and better convergent accuracy for the unsupervised training. The existing plain PINN enforces all the physics laws via the loss functions and the network tends to have very slow training speed and a large convergent error for large problems. An extreme learning machine (ELM) is used for the networks in the first stage. Compared with fully connected network (FCN) trained by the traditional back-propagation algorithm, ELM can be easily trained and converges much faster. Furthermore, by leveraging the differential nature of the DNN model, we can directly estimate the derivative of the cooling heat flux with respect to current density instead of using a finite difference approximation. The calculated derivatives are used to find the optimal current density to achieve maximum cooling heat flux via Newton’s method. Last but not least, we propose a novel hybrid finite element neural network (FENN) method to perform thermal analysis of the VLSI chip system with the TEC device. The DNN model is embedded into COMSOL through the heat flux boundary conditions. Experimental results show that the machine learning-based method can achieve about$8.5\times $speedup with good accuracy than the COMSOL-based finite element method. Furthermore, the proposed IPCNN is more stable and accurate than the existing PINN. The proposed FENN can have a$5.1\times $speedup and$5.4\times $memory reduction over the traditional numerical method.

2.5D chiplet-based technology promises an efficient integration technique for advanced designs with more functionality and higher performance. Temperature and related thermal optimization, heat removal are of critical importance for temperature-aware physical synthesis for chiplets. This paper presents a novel graph convolutional networks (GCN) architecture to estimate the thermal map of the 2.5D chiplet-based systems with the thermal resistance networks built by the compact thermal model (CTM). First, we take the total power of all chiplets as an input feature, which is a global feature. This additional global information can overcome the limitation that the GCN can only extract local information via neighborhood aggregation. Second, inspired by convolutional neural networks (CNN), we add skip connection into the GCN to pass the global feature directly across the hidden layers with the concatenation operation. Third, to consider the edge embedding feature, we propose an edge-based attention mechanism based on the graph attention networks (GAT). Last, with the multiple aggregators and scalers of principle neighborhood aggregation (PNA) networks, we can further improve the modeling capacity of the novel GCN. The experimental results show that the proposed GCN model can achieve an average RMSE of 0.31 K and deliver a 2.6× speedup over the fast steady-state solver of open-source HotSpot based on SuperLU. More importantly, the GCN model demonstrates more useful generalization or transferable capability. Our results show that the trained GCN can be directly applied to predict thermal maps of six unseen datasets with acceptable mean RMSEs of less than 0.67 K without retraining via inductive learning.

Temperature gradient due to Joule heating has huge impacts on the electromigration (EM) induced failure effects. However, Joule heating and related thermomigration (TM) effects were less investigated in the past for physics-based EM analysis for VLSI chip design. In this work, we propose a new spatial temperature aware transient EM induced stress analysis method. The new method consists of two new contributions: First, we propose a new TM-aware void saturation volume estimation method for fast immortality check in the post-voiding phase for the first time. We derive the analytic formula to estimate the void saturation in the presence of spatial temperature gradients due to Joule heating. Second, we develop a fast numerical solution for EM-induced stress analysis for multi-segment interconnect trees considering TM effect. The new method first transforms the coupled EM-TM partial differential equations into linear time-invariant ordinary differential equations (ODEs). Then extended Krylov subspace-based reduction technique is employed to reduce the size of the original system matrices so that they can be efficiently simulated in the time domain. The proposed method can perform the simulation process for both void nucleation and void growth phases under time-varying input currents and position-dependent temperatures. The numerical results show that, compared to the recently proposed semi-analytic EM-TM method, the proposed method can lead to about 28x speedup on average for the interconnect with up to 1000 branches for both void nucleation and growth phases with negligible errors.

Electromigration (EM) becomes a major concern for VLSI circuits as the technology advances in the nanometer regime. The crux of problem is to solve the partial differential Korhonen equations, which remains challenging due to the increasing integrated density. Recently, scientific machine learning has been explored to solve partial differential equations (PDE) due to breakthrough success in deep neural networks and existing approach such as physics-informed neural networks (PINN) shows promising results for some small PDE problems. However, for large engineering problems like EM analysis for large interconnect trees, it was shown that the plain PINN does not work well due the to large number of variables. In this work, we propose a novel hierarchical PINN approach, HierPINN-EM for fast EM induced stress analysis for multi-segment interconnects. Instead of solving the interconnect tree as a whole, we first solve EM problem for one wire segment under different boundary and geometrical parameters using supervised learning. Then we apply unsupervised PINN concept to solve the whole interconnects by enforcing the physics laws in the boundaries for all wire segments. In this way, HierPINN-EM can significantly reduce the number of variables at plain PINN solver. Numerical results on a number of synthetic interconnect trees show that HierPINN-EM can lead to orders of magnitude speedup in training and more than 79× better accuracy over the plain PINN method. Furthermore, HierPINN-EM yields 19% better accuracy with 99% reduction in training cost over recently proposed Graph Neural Network-based EM solver, EMGraph.

In this article, electrothermal modeling and simulation of thermoelectric cooling (TEC) in the package design of VLSI systems are performed by solving coupled heat conduction and current continuity equations. We propose a new analytical solution to the coupled partial differential equations (PDEs) which describe temperature and voltage with the reduction from 3-D to 1-D. In addition to this, we derive new analytic expressions for two key performance metrics for TEC devices: 1) the maximum temperature difference and 2) the maximum heat-flux pumping capability, which can be guided for the optimal design of thermoelectric cooler to achieve the maximum cooling performance. Furthermore, for the first time, we observe that when the dimensionless figure of merit$ZT_{0}$value is larger than 1, there is no maximum heat-flux value, which means the heat dissipation due to the Peltier and Fourier transfer effects is larger than the heat generation caused by the Joule heating effect, which can lead to more efficient TEC cooling design. The accuracy of the proposed 1-D formulas is verified by a 3-D finite element method using COMSOL software. The compact model delivers many orders of magnitude speedup and memory saving compared to COMSOL with marginal accuracy loss. Compared with the conventional simplified 1-D energy equilibrium model, the proposed analytical coupled multiphysics model is more robust and accurate.

Electromigration (EM) becomes a major concern for VLSI circuits as the technology advances in the nanometer regime. With Korhonen equations, EM assessment for VLSI circuits remains challenged due to the increasing integrated density. VLSI multisegment interconnect trees can be naturally viewed as graphs. Based on this observation, we propose a new graph convolution network (GCN) model, which is called EMGraph considering both node and edge embedding features, to estimate the transient EM stress of interconnect trees. Compared with recently proposed generative adversarial network (GAN) based stress image-generation method, EMGraph model can learn more transferable knowledge to predict stress distributions on new graphs without retraining via inductive learning. Trained on the large dataset, the model shows less than 1.5% averaged error compared to the ground truth results and is orders of magnitude faster than both COMSOL and state-of-the-art method. It also achieves smaller model size, $4\times$ accuracy and $14\times$ speedup over the GAN-based method.

Considering temperature gradient or thermomigration (TM) impacts on electromigration (EM) due to Joule heating was less studied in the past. In this article, we propose a new semi-analytical stress transient analysis method to consider both EM and TM effects for general multisegment interconnects. The new method is based on the separation of variables (SOVs) approach to find the analytic solution of coupled EM-TM partial differential equation (PDE). The algorithm consists of several steps. We first develop analytic solutions to compute the steady-state temperature distribution of multisegment wires. Based on this, we derive closed-form solutions for steady-state hydrostatic stress distribution in the context of thermal gradients due to Joule heating for multisegment interconnect wires. With the steady-state stress distribution, the coupled EM-TM PDE can be homogenized and solved by the SOV method. To deal with temperature/position-dependent diffusivity of metal migration process due to nonuniform temperature distribution, we utilize a piecewise linear technique to approximate the position-dependent diffusivity. The numerical results on multisegment interconnects show that the proposed method has negligible error loss compared to commercial finite element analysis software COMSOL but is about an order of magnitude faster than COMSOL with 10× less memory footprint. The numerical results further show that temperature gradient due to Joule heating indeed has significant impacts on the EM failure process.

Electromigration (EM) becomes one of the most challenging reliability issues for current and future ICs in 10-nm technology and below. In this article, a novel method is proposed for the EM hydrostatic stress analysis on 2-D multibranch interconnect trees, which is the foundation of the EM reliability assessment for large-scale on-chip interconnect networks, such as on-chip power grid networks. The proposed method, which is based on an eigenfunction technique, could efficiently calculate the hydrostatic stress evolution for multibranch interconnect trees stressed with different current densities and nonuniformly distributed thermal effects. The proposed method solves the partial differential equations of transient EM stress more efficiently since it does not require any discretization either spatially or temporally, which is in contrast to numerical methods, such as the finite difference method and finite element method. The accuracy of the proposed transient analysis approach is validated against the analytical solution and commercial tools. The convergence of the proposed method is demonstrated by numerical experiments on practical power/ground networks, showing that only a small number of eigenfunction terms are necessary for the accurate solution. Thanks to its analytical nature, the proposed method is also utilized in efficient EM analysis techniques, such as searching for the void nucleation time by a modified bisection algorithm. The numerical results show that the proposed method is 10X-100X faster than the finite difference method and scales better for larger interconnect trees.

In this paper, an adaptive algorithm is proposed to perform electromigration (EM) assessment for full-chip power/ground networks. Based on the eigenfunction solutions, the proposed method improves the efficiency by properly selecting the eigenfunction terms and utilizing the closed-form eigenfunctions for commonly seen interconnect wires such as T-shaped or cross-shaped wires. It is demonstrated that the proposed method can trad-off well among the accuracy, efficiency and applicability of the eigenfunction based methods. The experimental results show that the proposed method is about three times faster than the finite difference method and other eigenfunction based methods.

Electromigration (EM) is still the most important reliability concern for VLSI systems, especially at the nanometer regime. EM immortality check is an important step for full-chip EM signoff analysis. In this paper, we propose a new electromigration (EM) immortality check method for multi-segment interconnect considering the impacts of Joule heating induced temperature gradient. Temperature gradients from metal Joule heating, called thermal migration, can be a significant force for the metal atomic migrations, and these impacts get more significant as technology scales down. Compared to existing methods, the new method can consider the spatial temperature gradient due to Joule heating for multi-segment wires for the first time. We derive the analytic solution for the resulting steady-state EM-thermal migration stress distribution problem. Then we develop the new temperature-aware voltage-based EM immortality check method considering the multi-segment temperature migration effects, which carries all the benefits of the recently proposed voltage-based EM immortality method for multi-segment interconnects. Numerical results on an IBM power grid and self synthesized power delivery networks show that the proposed temperature-aware EM immortality check method is much more accurate than recently proposed state of the art EM immortality method.

Electromigration (EM) is considered to be one of the most important reliability issues for current and future ICs in 10-nm technology and below. In this article, we propose a fast analytic solution to compute the stress evolution in the confined multisegment interconnect wires. The new method, called the accelerated separation of variables (ASOV) method, aims to find the analytic solutions of the partial differential equations of stress in confined interconnect metals based on the SOV method. It offers several improvements over the existing plain SOV-based method. First, we show that the accuracy of the solution depends on the structure of the interconnects. As a result, the number of required eigenvalues is structure and problem dependent, instead of fixed numbers used by the existing SOV method. Second, for the straight line multisegment and star-structured multiterminal interconnects, analytical expressions are formulated to calculate the eigenvalues directly instead of using numerical methods as in the existing SOV method. Third, we propose a linear Gaussian elimination (GE) algorithm by exploiting the banded structure with the serrated-edge form of the transcendental matrix, which can significantly speed up GE process, and is the key computing step in the SOV-based solution framework. Fourth, instead of using the simple bisection search, we propose to use an enhanced determinant-based secant iterative method to find the eigenvalues of the transcendental matrix. Numerical results show that a good agreement is achieved between analytical and numerical results on two special cases, and the resulting algorithm can lead to 3-5X speedup over the existing plain SOV-based solution on a number of multisegment interconnects benchmarks.