Environmental monitoring applications often require 24/7 operation in harsh, low resource (e.g. power and communication) environments over a large scale area with ad-hoc deployment of sensors. Data processing at the sensor is required to minimize communication overhead. Such an application scenario presents opportunities for research in wireless sensor networks (WSN)s that are distinct from existing commercial off-the-shelf (COTS) solutions. We present a novel modular, highly flexible, hardware solution with a core feature of a System on a Chip (SoC) with add-ons such as memories, interfaces, and different transmission input/output I/O modalities. The system can manage, process, and transmit data directly within an ad-hoc self healing, self forming, mesh network over long distance (19 km between nodes in the current implementation) or as a stand-alone system. Hardware has been produced and the system has been validated in real-world deployments.

We describe a unified approach to scheduling point-to-point uni-directional communications among concurrent FPGA-based hardware processes. In this model, processes have separate address spaces, and share data through communication. Once a channel is written, it may not be re-written until the receiving process reads the data. Thus if the writer process is ready before the reader has read the previous message, the writer must stall. We present an algorithm to automatically generate synchronized hardware schedules for the parallel processes that communicate, so that hardware stall management is not required. The algorithm requires that the parallel processes conform to certain constraints in program control structures and communications forms. If the processes do not conform to these requirements, hardware-supported stall mechanisms are used. We quantify the impact in area and clock speed between compiler-generated synchronization of process schedules and run-time, hardware-mediated synchronization.

This paper presents a method to detect gamma-ray pulsars using a fast folding algorithm (Staelin, 1969) mapped onto reconfigurable hardware. In contrast, existing techniques require gigapoint complex FFTs. the algorithm has been written in Streams-C and compiled with the sc2 compiler to the target Annapolis Micro Systems (AMS) Firebird board (Xilinx Virtex E processor). To accelerate detection of new gamma-ray pulsars, the sc2 compiler generates a hardware implementation of the algorithm for finding periodicities in data sets. The data to be analyzed comes from a high-energy gamma-ray telescope onboard a spacecraft. This astrophysics application poses a "good example" of the use of a high level reconfigurable computing tool such as sc2 to accelerate an algorithm because it uses real satellite data, the algorithm can be parallelized, and was originally validated using a high level scientific language, IDL. By recasting the algorithm into Streams-C, the scientific software developer can create a hardware implementation on a reconfigurable computing platform. We describe the fast folding algorithm, the Streams-C implementation, and discuss techniques to optimize performance within the Streams-C framework. The compiler-generated hardware delivers approximately 3X to 6X speed up over a comparable 800MHz general-purpose processor doing the software-only algorithm.

The Streams-C compiler ([5]) synthesizes hardware circuits for reconfigurable FPGA-based computers from parallel C programs. The Streams-C language consists of a small number of libraries and intrinsic functions added to a synthesizable subset of C, and supports a communicating process programming model. The processes may be either software or hardware processes, and the compiler manages communication among the processes transparently to the programmer. For the hardware processes, the compiler generates Register-Transfer-Level (RTL) VHDL, targeting multiple FPGAs with dedicated memories. For the software processes, a multi-threaded software program is generated.