This paper presents a fault-tolerant event detection scheme for wireless sensor networks. Unlike others using a single threshold, the proposed scheme employs two thresholds to cope with the trade-off between event detection accuracy and false alarm rate. An extremely low false alarm rate can be achieved by using a high threshold, while high detection accuracy is obtained by using a low threshold. A sensor node is determined to be in an event region if it passes the high threshold. It can also be determined to be in the region, as long as it passes the low threshold and has a neighbor that passes the high threshold. The dissemination of a local decision to neighboring nodes is made only once to minimize the communication overhead. A moving average filter with a threshold is employed to reduce the impact of transient faults in sensor readings. Computer simulation shows that the proposed scheme also achieves acceptable performance in detecting event regions without computational overhead.

Bloom filters can be used for various networking applications to inspect network packet payload to search for predefined signature strings. Hardware-based bloom filters have drawn a great attention due to the fact that they provide constant lookup times at the cost of small false positives. A fault in bloom filters, however, may render the system unable to function correctly since no false negatives cannot be guaranteed. In this paper, we present a fault- tolerant bloom filter which tolerates faults in such a way that no false negatives can be guaranteed. The proposed architecture is simple enough to be implemented without any significant hardware overhead. Moreover, fault detection and recovery can be made during normal operation with negligible time overhead.

Secure transmission over wireline/wireless networks requires encryption of data and control information. For high-speed data transmission, it would be desirable to implement the encryption algorithms in hardware. Faults in the hardware, however, may cause interruption of service and side-channel attacks. This paper presents a simple technique for achieving fault tolerance in pipelined implementation of symmetric block ciphers. It detects errors, locates the corresponding faults, and readily reconfigures during normal operation, to isolate the identified faulty modules. Bypass links with some extra pipeline stages are used to achieve fault tolerance. The hardware overhead can be controlled by properly choosing the number of extra stages. Moreover, fault tolerance is achieved with negligible time overhead.

We present an algorithm based error detection technique for a real time cell scheduler in ATM switches. The scheduler is designed to realize EDF (earliest deadline first) scheduling to guarantee the end to end delay bounds of real time messages. The algorithm invariants of the scheduler are identified to detect erroneous or out of order cell transmissions due to a malfunctioning scheduler. Since a malfunctioning scheduler is unlikely to produce errors detectable at the host level, an immediate detection and recovery at each switch is highly desirable in order to achieve reliable communication in ATM networks. The hardware overhead for realizing error detection is manageably small. Moreover, error detection can be done locally with negligible time overhead.

In this paper, we present a concurrent error detection and fault location technique for a fast ATM switch. The switch architecture has multiple data and control planes, each of which has an identical banyan topology. Cell headers are routed via the control planes to reserve their routing paths on the data planes. Multiplicity of data planes for enhancing performance is utilized to detect errors and locate faults during normal operation. An efficient algorithm is developed to locate faulty links or switching elements while normal switching operations are being performed. The identified faulty data planes can also be made usable for cell transmission.

In this paper, we present a test structure for identifying faulty processing or switching nodes in massively parallel processing systems. The structure does not require any precomputed and stored responses. It is based on group probing and leads to a high test performance by exploiting parallelism in testing. Once a fault is detected, the expected response is obtained by finding a dominant group of nodes producing an identical response. The response from the dominant group is then broadcast to all the nodes under test to determine their fault status by a local comparison. The technique can be used to test identical chips or processing nodes regardless of how the test vectors are generated.

In a board level design with boundary scans, each chip on a board can be tested by loading test vectors and collecting responses through a boundary scan chain. Since the boundary scan may serialize the test process, the overall test time can be reduced if multiple boundary scan chains are used. In that case the test time depends on how the boundary scan chips are connected into multiple chains. In this paper, we present a technique for configuring multiple boundary scan chains to minimize the test time for boundary scan chips on a board.

Testing of boards containing a mixture of boundary scan components and clusters of non-boundary scan devices is considered. If a tester cannot contact the non-scan circuitry, the inputs and outputs of onboard boundary scan devices may be used as virtual tester pins. In this case, the time for testing the clusters depends on how the boundary scan chips are connected into a longer scan chain. A technique for configuring a chain of boundary scan chips to minimize the test time for clusters is presented.>

The authors propose a VLSI layout strategy for a full binary tree. This layout can support more border leaf processing elements (PEs) and thus can give a higher I-O bandwidth. It is superior to the H-tree layout in terms of the number of boundary leaves. The approach uses H-tree pattern for constructing subtree layouts and then combines a number of such subtrees following standard tree style to get a larger sized tree layout. Finally at the top level H-tree layout style is used to get the overall tree layout. Different I/O bandwidths can be obtained varying the subtree height. The authors derive expression for layout area, longest link and aspect ratio of the chip. It is observed that I/O bandwidth can be significantly increased without much area overhead using this approach.>

Cube connected cycles (CCC), a popular and layout/efficient alternative to hypercube, can emulate the performance of hypercube for many parallel algorithms. Recently, interconnection networks based on simplex links rather than duplex have been proposed. The uni-directional architectures have layout advantages and reduces complexity of each processing element (PE). The authors propose directed cube connected cycles (DCCC) as a uni-directional alternative to CCC. They have developed PE-to-PE routing algorithm for DCCC. A method for porting algorithms (designed to run on bi-directional CCC) to DCCC is provided. The extent of slowdown due to using simplex links is evaluated. They also provide loop embedding on DCCC. DCCC is found competitive to CCC in algorithmic performance though DCCC is much layout inexpensive.>

A method is proposed for achieving fault tolerance by introducing a redundant stage for a special-purpose fast Fourier transform (FFT) processor. A concurrent error-detection technique, called recomputing by alternate path, is used to detect errors during normal operation. Once an error is detected, a faulty butterfly can be located with log (N+5) additional cycles. The method has 100% detection and location capability, regardless of the magnitude of the roundoff errors. A gracefully degraded reconfiguration using a redundant stage is introduced. This technique ensures a high improvement in reliability and availability. Hardware overhead is O(1/log N) with some additional comparators and switches. The method can be applied to other algorithms implementable on the butterfly structure.>

A fault-tolerant systolic sorter design is proposed. An algorithm-based fault tolerance is achieved by testing the invariants of a systolic sorter during normal operation. Transient and permanent computation errors can be detected by using error-checking code and some redundant cells. A block with a single faulty cell can be located. Small hardware overhead and negligible time overhead are shown to be the major advantages of the method. A hierarchical structure is suggested as an efficient architecture for realizing the method. An offline fault-testing method for permanent stuck-at faults is presented.>